Protocol Configuration Register; Core Status Register - Xilinx Vivado MIPI CSI-2 Product Manual

Protocol Configuration Register

The Protocol Configuration register is described in
protocol specific options such as the number of lanes to be used.
Table 2-9: Protocol Configuration Register (0x04)
Bits Name
31–5 Reserved
4–3 Maximum Lanes
2 Reserved
1–0 Active Lanes
Notes:
1. Maximum Lanes cannot exceed the number of lanes as set by the Serial Data Lanes parameter at generation time.
2. A read from this register reflects the current number of lanes being used by core. This is useful when dynamically
updating the active lanes during core operation to ensure that the core is using the new active lanes information.
See Chapter 3, Designing with the Subsystem
3. Active Lanes cannot exceed the Maximum Lanes as set in the Protocol Configuration register setting of bits 4–3.

Core Status Register

The Core Status register is described in
Table 2-10: Core Status Register (0x10)
Bits
31–16 Packet Count
15–4 Reserved
3 Short packet FIFO Full
2 Short packet FIFO not empty
MIPI CSI-2 RX Subsystem v4.0
PG232 July 02, 2019
Reset Value
N/A
Number of lanes configured
(1)
during core generation
N/A
Number of lanes configured
during core generation
for more information.
Name Reset Value Access
0x0
N/A
0x0
0x0
www.xilinx.com
Chapter 2: Product Specification
Table 2-9 and allows you to configure
Access
N/A Reserved
Maximum lanes of the core
R
Reserved
Active lanes in the core
(2)
R /W
Table 2-10.
Counts number of long packets written to
the line buffer
R • No roll-over of this counter reported/
supported
• Count includes error packets (if any)
N/A N/A
Indicates the current status of short packet
R
FIFO full condition
FIFO not empty: Indicates the current status
R
of short packet FIFO not empty condition
Description
0x0—1 Lane
0x1—2 Lanes
0x2—3 Lanes
0x3—4 Lanes
(3)
0x0—1 Lane
0x1—2 Lanes
0x2 —3 Lanes
0x3—4 Lanes
Description
Send Feedback
25