I2S Transmitter Register Space - Xilinx I2S Product Manual

Table 1: Port Names (cont'd)
Port Name
Irq
lrclk_out
sclk_out
lrclk_in
Sclk_in
sdata_0_in
sdata_1_in
sdata_2_in
sdata_3_in
Notes:
1. For more details on Audio AXIS interface, see

I2S Transmitter Register Space

:
Note The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is
not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address
Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.
Table 2: Register Address Space
PG308 (v1.0) April 4, 2018
I2S Transmitter and I2S Receiver
I/O
O
O
O
I
I
I
I
I
I
Audio AXIS
Address (hex)
0x00
0x04
0x08
0x10
0x14
0x20
0x30
0x34
0x38
0x3C
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Chapter 3: Product Specification
Clock
Interrupt Active-High interrupt
LRClk Output LR Clock. Available when core is configured
as Master
SCLK Output SCK Clock. Available when core is
configured as Master
LRClk Input LR Clock. Available when core is configured
as Slave
SCLK Input SCK Clock. Available when core is configured
as Slave
SDATA0 I2S Serial Data In
SDATA1 I2S Serial Data In. Available when number of audio
channels is > 2
SDATA2 I2S Serial Data In. Available when number of audio
channels is > 4
SDATA3 I2S Serial Data In. Available when number of audio
channels is > 6
Interface.
Register Name
Core Version: Returns the core Major and Minor version
Core Configuration: Returns the core configuration details
Core Control: Register to enable/disable the core
Interrupt Control: Interrupt enable/disable register
Interrupt Status: Interrupt Status register
I2S Timing Control: Register to program the SCK divider
value
Channel 0/1 Control: Channel 0/1 control register
Channel 2/3 Control: Channel 2/3 control register
Channel 4/5 Control: Channel 4/5 control register
Channel 6/7 Control: Channel 6/7 control register
Description
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