Xilinx Vivado MIPI CSI-2 Product Manual page 7

X-Ref Target - Figure 1-2
PHY Protocol
PPI
Interface
(PPI)
AXI4-Lite
Register
Interface
Interrupt
Features of this core include:
• 1–4 lane support, with register support to select active lanes (the actual number of
available lanes to be used)
• Short and long packets with all word count values supported
• Primary and many secondary video formats supported
• Data Type (DT) interleaving
• Virtual Channel Identifier (VC) interleaving
• Combination of Data Type and VC interleaving
• Multi-lane interoperability
• Error Correction Code (ECC) for 1-bit error correction and 2-bit error detection in
packet header
• CRC check for payload data
• Long packet ECC/CRC forwarding capability for downstream IPs
• Maximum data rate of 2.5 Gb/s
• Pixel byte packing based on data format
• AXI4-Lite interface to access core registers
• Low power state detection
• Error detection (D-PHY Level Errors, Packet Level Errors, Protocol Decoding Level Errors)
• AXI4-Stream interface with 32/64-bit TDATA width support to offload pixel information
externally
• Interrupt support for indicating internal status/error information
MIPI CSI-2 RX Subsystem v4.0
PG232 July 02, 2019
Lane Control
Management FSM
Figure 1-2: MIPI CSI-2 RX Controller Core
www.xilinx.com
PHECC
Processing
Data
Buffer
Processing
CRC
Checker
Chapter 1: Overview
AXI4-Stream
AXI4-
Stream
X16317-031116
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