Sub-Core Details; Mipi D-Phy; Rx Controller; Chapter 1: Overview - Xilinx Vivado MIPI CSI-2 Product Manual

Sub-Core Details

MIPI D-PHY

The MIPI D-PHY IP core implements a D-PHY RX interface and provides PHY protocol layer
support compatible with the CSI-2 RX interface. The MIPI D-PHY IP core also supports the
deskew pattern detection for line rates >1.5 Gb/s. See the MIPI D-PHY LogiCORE IP Product
Guide (PG202)
devices and the 7 Series devices with respect to I/O.
For UltraScale+ devices, the Vivado IDE provides a
required I/O. However, for the 7 series devices the clock capable I/O should be selected
manually. In addition, the 7 series devices do not have a native MIPI IOB support. You will
have to target either HR bank I/O or HP bank I/O for the MIPI IP implementation. For more
information on MIPI IOB compliant solution and guidance, refer D-PHY Solutions (XAPP894)
[Ref 15].
MIPI CSI-2 RX Controller
The MIPI CSI-2 RX Controller core consists of multiple layers defined in the MIPI CSI-2 RX
1.1 specification, such as the lane management layer, low level protocol and byte to pixel
conversion.
The MIPI CSI-2 RX Controller core receives 8-bit data per lane, with support for up to 4
lanes, from the MIPI D-PHY core through the PPI. As shown in
received on the PPI is then processed by the low level protocol module to extract the real
image information. The final extracted image is made available to the user/processor
interface using the AXI4-Stream protocol. The lane management block always operates on
32-bit data received from PPI irrespective number of lanes.
MIPI CSI-2 RX Subsystem v4.0
PG232 July 02, 2019
[Ref 3] for details. MIPI D-PHY implementation differs for the UltraScale+
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Chapter 1: Overview

Pin Assignment Tab to select the
Figure 1-1
Send Feedback
the byte data
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