Register Space - Xilinx LogiCORE IP Product Manual

Table 2‐13: AXI4‐Lite Interface Signals (Cont'd)
Signal Name
s_axi_bvalid
s_axi_awready
Register Space
The SMPTE2022-5/6 Video over IP Receiver register space is partitioned to General and
Channel specific registers. See the SMPTE 2022-5/6 reference design for more information
on register usage.
Table 2‐14: AXI4‐Lite Register Map
Address
Register Name
(hex)
0x000 CONTROL
0x004 RESET
0x030 CHANNEL
0x03C VERSION
0x050 AXI_MM_ADDR_MSB
0x0A0 NUM_CHAN
LogiCORE IP SMPTE2022‐5/6 RX v2.1
PG033 December 18, 2012
Direction Width Description
AXI4-Lite Write Response Channel Response Valid.
Out 1
Indicates response is valid.
Out 1 AXI4-Lite Write Address Channel Write Address Ready.
Access
Type
General Registers
R/W
R/W
R/W
R
R/W
R
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Chapter 2: Product Specification
Default
Register Description
Value
Bit 0: Reserved
0 Bit 1: Register update
Bit 31-2: Reserved
Bit 0: Soft reset
0
Bit 31-1: Reserved
0 Bit 31-0: Access channel
Bit 7-0: Revision number
Bit 11-8: Patch ID
0x02010000 Bit 15-12: Version revision
Bit 23-16: Version minor
Bit 31-24: Version major
Bit 2-0: Most significant three bits
of the 32-bit AXI memory map
address to access the DDR through
0
the AXI interconnect
Bit 31-3: Reserved
Bit 10-0: Number of channels
0
Bit 31-11: Reserved
22