Ecc/Crc Forwarding; Vcx Support - Xilinx Vivado MIPI CSI-2 Product Manual

As shown in Table 1-1
interface data width is selected based on the Data Type selected.
Table 1-1: Embedded Non-Image AXI4-Stream Interface TDATA Widths
Data Type (DT)
YUV 422 8–bit
YUV 422 10–bit
Abrupt termination events such as a soft reset, disabling a core while a packet is being
written to the line buffer, or a line buffer full condition results in early termination. The
termination is implemented by assertion of EOL on the video interface or TLAST and
TUSER[1] on the embedded non-image interface, based on the current long packet being
processed.

ECC/CRC Forwarding

Sideband signals of AXI4-Stream interface [Include/Exclude Video Format Bridge and
Embedded non-image interface] report ECC and CRC data received from the source [sensor]
to downstream IPs. This allows to re-calculate ECC/CRC by the downstream IPs in certain
functional safety applications. See
In error scenarios like abrupt termination due to soft reset, disabling the core while packet
transfer in progress, line buffer in full condition, word count of received packet is greater
than the actual payload, these sideband signals do not report the correct ECC and CRC.

VCX Support

The MIPI CSI-2 standard v2.0 specific VCX support feature is used to extend the maximum
number of available virtual channels to 16. When this feature is enabled, the virtual channel
is deduced by combining the 2-bit VC field (LSB) and the 2-bit VCX field (MSB) from the
packet header.
MIPI CSI-2 RX Subsystem v4.0
PG232 July 02, 2019
the embedded non-image (with data type code 0x12) AXI4-Stream
RAW6
RAW7
RAW8
RAW10
RAW12
RAW14
RAW16
RAW20
All RGB
Port Descriptions
www.xilinx.com
AXI4-Stream Interface TDATA Width
32
32
32
64
64
64
64
64
64
64
64
for details on signal mapping.
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Chapter 1: Overview
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