Pca9554 Register 1 - Output Port Register; Pca9554 Register 2 - Polarity Inversion Register - Advantech ITA-5831 Series User Manual

6.2.3 PCA9554 Register 1 – Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Regis-
ters 3. Bit values in this register have no effect on pins defined as inputs. Reads from
this register return the value that is in the fili-flop controlling the output selection, not
the actual pin value.
Table 6.5: Register 1 – Output Port register bit description
Bit Symbol
7 O7
6 O6
5 O5
4 O4
3 O3
2 O2
1 O1
0 O0
If one GPIO Pin is set to Output, you can read input value from the bit that register 1
corresponds to.
6.2.4 PCA9554 Register 2 – Polarity Inversion register
The register allows the user to invert the polarity of the Input Port register data. If a bit
in this register is set (write with '1'), the corresponding Input Port data is inverted. If a
bit in this register is cleared (write with '0'), the Input Port data polarity is retained.
Table 6.6: Register 2 – Polarity Inversion register bit description
Bit Symbol Access
7 N7
6 N6
5 N5
4 N4
3 N3
2 N2
1 N1
0 N0
If one GPIO Pin is set to Input, you can control the polarity of input pin from the bit
that register 2 corresponds to.
ITA-5831 User Manual
Access Value
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
Value Description
R/W 0* Invert polarity of Input Port register data
R/W 0*
R/W 0* 0= Input Port register data retained (Default value)
R/W 0*
R/W 0* 1= Input Port register data inverted
R/W 0*
R/W 0*
R/W 0*
62
Description
Determined by externally applying logic level