Advantech ITA-5831 Series User Manual page 74

Intel the 6rd generation core i processor fanless system for railway applications
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Function call for reference:
......................................................................................................................................
ICH SMBUS Access Code
(The following code is realized by simulating the access of BIOS to
SMBUS. It uses Borand C++.
3.1 for compiling and is successfully tested under DOS (But it is not
tested under other OSs).
#define SMBUS_PORT 0xF040 //SMB_BASE is 0xF040
typedefunsigned char BYTE;
/////////////////////////////////////////////////////////////////////
BYTE
smbus_read_byte(BYTE addr, BYTE offset)
//Read SMBUS Register byte value. Read one byte value each time. ddr
is slave
address (such as 0x40), and offset is register offset.
{
int i;
BYTE data;
outportb(SMBUS_PORT + 4, (addr | 1)); //Write slave address to
SMB_BASE + 4 (When reading, bit 0 of slave address should be set as 1,
so here addr|1 is available)
newiodelay();
newiodelay();
chk_smbus_ready(); //Whether SMBUS is ready
outportb(SMBUS_PORT + 3, offset);//Write register offset to
SMB_BASE
+3.
newiodelay();
newiodelay();
outportb(SMBUS_PORT + 2, 0x48); //Write
SMB_BASE + 2. 0x48 means starting byte data transmission
newiodelay();
newiodelay();
for (i = 0; i <= 0x100;
{
}
ITA-5831 User Manual
//delay
//delay
//delay
//delay
//delay
//delay
newiodelay();
SMBUS
i++)
//longerdelay
64
command
to

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