Advantech ITA-5831 Series User Manual page 75

Intel the 6rd generation core i processor fanless system for railway applications
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chk_smbus_ready(); //wheater SMBUS is ready return
(inportb(SMBUS_PORT + 5)); // Byte value read from SMB_BASE + 5
}
/////////////////////////////////////////////////////////////////////
void smbus_write_byte(BYTE addr, BYTE offset, BYTE value)
// Write SMBUS Register byte value. Write one byte value each time.
addr is slave address (such as 0x40), and offset is register offset
{
int i;
outportb(SMBUS_PORT + 4, addr); //
SMB_BASE + 4 (When writing, slave address bit 0 should be set as 0)
moredelay();
moredelay();
chk_smbus_ready(); //wheater SMBUS is ready
outportb(SMBUS_PORT + 3, offset);// write register offset to
SMB_BASE
+3.
moredelay();
moredelay();
outportb(SMBUS_PORT + 5, value);//
SMB_BASE + 5
moredelay();
moredelay();
outportb(SMBUS_PORT + 2, 0x48); //
SMB_BASE + 2.. 0x48 means starting byte data transmission.
moredelay();
moredelay();
for (i = 0; i <= 0x100; i++)
{
newiodelay();//longerdelay
}
chk_smbus_ready(); //wheater SMBUS is ready
}
Write
//longerdelay
//longerdelay
//longerdelay
//longerdelay
Write
//longerdelay
//longerdelay
Write
//longerdelay
//longerdelay
65
slave
address
to
data
value
to
SMBUS
command
to
ITA-5831 User Manual

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