Atmel SAM4SD32B Preliminary Data Sheet page 680

Figure 32-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address
TWI_THR = data to send
SAM4S Series [Preliminary]
680
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Yes
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Yes
Data to send?
Yes
Write STOP Command
TWI_CR = STOP
Read Status register
Yes
TXCOMP = 1?
END
(if IADR used)
No
Set the internal address
TWI_IADR = address
No
No
11100B–ATARM–31-Jul-12