Atmel SAM4SD32B Preliminary Data Sheet page 672

32.8 Master Mode
32.8.1 Definition
32.8.2 Application Block Diagram
32.8.3 Programming Master Mode
32.8.4 Master Transmitter Mode
SAM4S Series [Preliminary]
672
The Master is the device that starts a transfer, generates a clock and stops it.
Figure 32-5. Master Mode Typical Application Block Diagram
TWD
Host with
TWI
TWCK
Interface
Atmel TWI
Serial EEPROM
Slave 1
Rp: Pull up value as given by the I²C Standard
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
to access slave devices in read or write mode.
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
After the master initiates a Start condition when writing into the Transmit Holding Register,
TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in
TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer
direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in
the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR.
TXRDY is used as Transmit Ready for the PDC transmit channel.
I²C LCD
I²C RTC
Controller
Slave 2 Slave 3
VDD
Rp Rp
I²C Temp.
Sensor
Slave 4
11100B–ATARM–31-Jul-12