Atmel SAM4SD32B Preliminary Data Sheet page 880

36.14.2 HSMCI Mode Register
Name: HSMCI_MR
Address: 0x40000004
Access: Read-write
31 30
– –
23 22
– –
15 14
PDCMODE PADV
7 6
This register can only be written if the WPEN bit is cleared in
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN
bit).
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0 = Disables Read Proof.
1 = Enables Read Proof.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0 = Disables Write Proof.
1 = Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
0 = Disables Force Byte Transfer.
1 = Enables Force Byte Transfer.
SAM4S Series [Preliminary]
880
29 28
– –
21 20
– –
13 12
FBYTE WRPROOF
5 4
CLKDIV
(PWSDIV)
27 26
– –
19 18
– –
11 10
RDPROOF
3 2
"HSMCI Write Protect Mode Register" on page
+ 1 when entering Power Saving Mode.
25 24
– –
17 16
– –
9 8
PWSDIV
1 0
903.
11100B–ATARM–31-Jul-12