Atmel SAM4SD32B Preliminary Data Sheet page 689

Figure 32-25. Read Access Ordered by a MASTER
TWI answers with a NACK
S ADR
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
32.10.5.2 Write Operation
Figure 32-26. Write Access Ordered by a Master
SADR does not match,
TWI answers with a NACK
S ADR
TWD
RXRDY
SVACC
SVREAD
EOSVACC
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
11100B–ATARM–31-Jul-12
SADR does not match,
R NA DATA NA
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 32-26 on page 689
W NA DATA NA
SAM4S Series [Preliminary]
SADR matches,
TWI answers with an ACK
P/S/Sr SADR R A DATA
Write THR
SVREAD has to be taken into account only while SVACC is active
describes the Write operation.
SADR matches,
TWI answers with an ACK
P/S/Sr SADR W A DATA
SVREAD has to be taken into account only while SVACC is active
ACK/NACK from the Master
A A DATA NA
Read RHR
A A DATA NA S/Sr
S/Sr
Read RHR
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