Atmel SAM4SD32B Preliminary Data Sheet

Atmel SAM4SD32B Preliminary Data Sheet

At91sam arm-based flash mcu
Table of Contents
  • Unknown

    • Features
    • Description
    • Configuration Summary
    • Advref
      • Signal Description
      • Package and Pinout
        • SAM4SD32/SD16/SA16/S16/S8C Package and Pinout
        • Table of Contents
    • Block Diagram
    • Pb0/Ad4
    • Pb1/Ad5
      • SAM4SD32/SD16/SA16/S16/S8 Package and Pinout
    • Pb2/Ad6
      • Power Considerations
        • Power Supplies
        • Voltage Regulator
        • Typical Powering Schematics
        • Active Mode
        • Low-Power Modes
        • Wake-Up Sources
        • Fast Startup
      • Input/Output Lines
        • General Purpose I/O Lines
        • System I/O Lines
        • Test Pin
        • NRST Pin
        • ERASE Pin
      • Product Mapping
      • Memories
        • Embedded Memories
        • External Memories
      • System Controller
    • Vddin
      • System Controller and Peripheral Mapping
        • Power-On-Reset, Brownout and Supply Monitor
      • Peripherals
    • Vddcore
    • Vddio
    • Vddcore
    • Pc28
    • Pa28
    • Pa29
    • Pa30
    • Pc11
    • Vddio

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Features

Core
®
®
– ARM
Cortex
-M4 with a 2 Kbytes cache running at up to 120 MHz
– Memory Protection Unit (MPU)
– DSP Instruction Set
®
– Thumb
-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S products (64- and 100- pin versions) and
SAM7S legacy products (64-pin version)
Memories
– Up to 2048 Kbytes embedded Flash with optional dual bank and cache memory
– Up to 160 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash
support
System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
– RTC with Gregorian and Persian Calendar mode, waveform generation in low-
power modes
– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 240 MHz for device clock and for USB
– Temperature Sensor
– Up to 22 Peripheral DMA (PDC) Channels
Low Power Modes
– Sleep and Backup modes, down to 1 µA in Backup mode
– Ultra low-power RTC
Peripherals
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
Transceiver
– Up to 2 USARTs with ISO7816, IrDA
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
– 2 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM
mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16-channel, 1Msps ADC with differential input mode and programmable gain
stage and auto calibration
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Write Protected Registers
I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch
0.8 mm/100-ball VFBGA, 7 x 7 mm, pitch 0.65 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-lead QFN 9x9 mm, pitch 0.5 mm
®
, RS-485, SPI, Manchester and Modem Mode
AT91SAM
ARM-based
Flash MCU
SAM4S Series
Preliminary
Datasheet
11100B–ATARM–31-Jul-12

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Summary of Contents for Atmel SAM4SD32B

  • Page 1: Features

    Features • Core ® ® – ARM Cortex -M4 with a 2 Kbytes cache running at up to 120 MHz – Memory Protection Unit (MPU) – DSP Instruction Set ® – Thumb -2 instruction set • Pin-to-pin compatible with SAM3N, SAM3S products (64- and 100- pin versions) and SAM7S legacy products (64-pin version) •...
  • Page 2: Description

    1. Description The Atmel SAM4S series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M4 RISC processor. It operates at a maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with optional dual bank implementation and cache memory, and up to 160 Kbytes of SRAM.
  • Page 3: Configuration Summary

    Configuration Summary The SAM4S series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the device family. Table 1-1. Configuration Summary Feature SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B 2 x 1024...
  • Page 4: Block Diagram

    2. Block Diagram Figure 2-1. SAM4S16, S8 Series 100-pin version Block Diagram System Controller Voltage Regulator PCK0-PCK2 PLLA Flash User JTAG & Serial Wire PLLB Unique Signature Identifier RC Osc 12/8/4 MHz In-Circuit Emulator 24-Bit 3-20 MHz SysTick Counter FLASH SRAM Cortex-M4 Processor XOUT...
  • Page 5 SAM4S Series [Preliminary] Figure 2-2. SAM4S16, S8 Series 64-pin version Block Diagram System Controller Voltage Regulator PCK0-PCK2 PLLA Flash User JTAG & Serial Wire Unique Signature PLLB Identifier RC Osc 12/8/4 MHz In-Circuit Emulator 24-Bit 3-20 MHz FLASH SRAM SysTick Counter Cortex-M4 Processor XOUT 1024 Kbytes...
  • Page 6 Figure 2-3. SAM4SD32, SD16, SA16 100-pin version Block Diagram T ST Voltage Regulator PCK0-PCK2 PLLA JTAG & Serial Wire PLLB Flash Unique 12/8/4 M Identifier In-Circuit Emulator 24-Bit 3-20 MHz SysTick Counter Cortex-M4 Processor Osc. X OUT FLASH SRAM Fmax 120 MHz 2*1024 KBytes 160 KBytes 16 KBytes...
  • Page 7 SAM4S Series [Preliminary] Figure 2-4. SAM4SD32, SD16, SA16 64-pin version Block Diagram System Controller Voltage Regulator PCK0-PCK2 PLLA Flash JTAG & Serial Wire Unique PLLB Identifier RC Osc 12/8/4 MHz In-Circuit Emulator 24-Bit 3-20 MHz SysTick Counter Cortex-M4 Processor FLASH XOUT SRAM Fmax 120 MHz...
  • Page 8: Signal Description

    3. Signal Description Table 3-1 gives details on signal names classified by peripheral. Table 3-1. Signal Description List Active Voltage Signal Name Function Type Level reference Comments Power Supplies Peripherals I/O Lines and USB transceiver VDDIO Power 1.62V to 3.6V Power Supply Voltage Regulator Input, ADC, DAC and VDDIN...
  • Page 9 SAM4S Series [Preliminary] Table 3-1. Signal Description List (Continued) Active Voltage Signal Name Function Type Level reference Comments Flash Memory Reset State: Flash and NVM Configuration Bits Erase - Erase Input ERASE Input High VDDIO Command - Internal pull-down enabled - Schmitt Trigger enabled Reset/Test Permanent Internal...
  • Page 10 Table 3-1. Signal Description List (Continued) Active Voltage Signal Name Function Type Level reference Comments Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data Input RTSx USARTx Request To Send Output CTSx USARTx Clear To Send Input...
  • Page 11 SAM4S Series [Preliminary] Table 3-1. Signal Description List (Continued) Active Voltage Signal Name Function Type Level reference Comments Two-Wire Interface- TWI TWDx TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock Analog ADC, DAC and Analog Comparator ADVREF Analog Reference 12-bit Analog-to-Digital Converter - ADC Analog, AD0-AD14...
  • Page 12: Package And Pinout

    4. Package and Pinout SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 64- and 100-pin ver- sions, and AT91SAM7S legacy products in 64-pin versions. SAM4SD32/SD16/SA16/S16/S8C Package and Pinout 4.1.1 100-Lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 4.1.2 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards.
  • Page 13 SAM4S Series [Preliminary] 4.1.3 100-ball VFBGA Package Outline Figure 4-3. Orientation of the 100-ball VFBGA Package 11100B–ATARM–31-Jul-12...
  • Page 14: Table Of Contents

    4.1.4 100-Lead LQFP Pinout Table 4-1. SAM4SD32/SD16/SA16/S16/S8C 100-lead LQFP pinout TDO/TRACESWO/ ADVREF TDI/PB4 VDDIO PA6/PGMNOE JTAGSEL PB0/AD4 PA16/PGMD4 PA5/PGMRDY PC18 PC29/AD13 PC28 TMS/SWDIO/PB6 PB1/AD5 PA15/PGMD3 PA4/PGMNCMD PC19 PC30/AD14 PA14/PGMD2 VDDCORE PA31 PB2/AD6 PA27/PGMD15 PC20 PC31 PA13/PGMD1 TCK/SWCLK/PB7 PB3/AD7 PA24/PGMD12 PA28 PC21 VDDIN NRST...
  • Page 15: Pb0/Ad4

    SAM4S Series [Preliminary] 4.1.5 100-Ball TFBGA Pinout Table 4-2. SAM4SD32/SD16/SA16/S16/S8 100-ball TFBGA pinout PA18/PGMD6/ PB1/AD5 TCK/SWCLK/PB7 PC29 PC16 PC26 PA11/PGMM3 VDDIO PA1/PGMEN1 VDDOUT PB9/PGMCK/XIN PC17 PA6/PGMNOE PB8/XOUT PA0/PGMEN0 VDDIO TDI/PB4 PB13/DAC0 PB3/AD7 PA27/PGMD15 PC15/AD11 DDP/PB11 PB0/AD4 DDM/PB10 PC24 PA28 PA16/PGMD4 TMS/SWDIO/PB6 PC22 JTAGSEL...
  • Page 16: Pb1/Ad5

    4.1.6 100-Ball VFBGA Pinout Table 4-3. SAM4SD32/SD16/SA16/S16/S8 100-ball VFBGA pinout ADVREF VDDOUT PA12/PGMD0 PA18/PGMD6/ VDDPLL TMS/SWDIO/PB6 PA9/PGMM1 PA17/PGMD5/ PB9/PGMCK/XIN PA1/PGMEN1 VDDCORE PB8/XOUT PA0/PGMEN0 PA6/PGMNOE PA5/PGMRDY JTAGSEL PC16 DDP/PB11 PB1/AD5 PC26 PA20/AD3 DDM/PB10 PC30 PA4/PGMNCMD PC12/AD12 PC20 PC31 PA28 PA16/PGMD4 PC19 PC22 TDO/TRACESWO/ PA24...
  • Page 17: Sam4Sd32/Sd16/Sa16/S16/S8 Package And Pinout

    SAM4S Series [Preliminary] SAM4SD32/SD16/SA16/S16/S8 Package and Pinout 4.2.1 64-Lead LQFP Package Outline Figure 4-4. Orientation of the 64-lead LQFP Package 4.2.2 64-lead QFN Package Outline Figure 4-5. Orientation of the 64-lead QFN Package TOP VIEW 11100B–ATARM–31-Jul-12...
  • Page 18: Pb2/Ad6

    4.2.3 64-Lead LQFP and QFN Pinout Table 4-4. 64-pin SAM4SD32/SD16/SA16/S16/S8 pinout TDO/TRACESWO/ ADVREF TDI/PB4 VDDIO PA6/PGMNOE JTAGSEL PB0/AD4 PA16/PGMD4 PA5/PGMRDY TMS/SWDIO/PB6 PB1/AD5 PA15/PGMD3 PA4/PGMNCMD PA31 PB2/AD6 PA14/PGMD2 PA27/PGMD15 TCK/SWCLK/PB7 PB3/AD7 PA13/PGMD1 PA28 VDDCORE VDDIN PA24/PGMD12 NRST ERASE/PB12 VDDOUT VDDCORE DDM/PB10 PA17/PGMD5/ PA25/PGMD13 PA29...
  • Page 19: Power Considerations

    SAM4S Series [Preliminary] 5. Power Considerations Power Supplies The SAM4S has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.08V to 1.32V. • VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup part, 32 kHz crystal oscillator and oscillator pads.
  • Page 20 Figure 5-1. Single Supply VDDIO Transceivers. Main Supply (1.62V-3.6V) ADC, DAC Analog Comp. VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Note: Restrictions For USB, VDDIO needs to be greater than 3.0V. For ADC, VDDIN needs to be greater than 2.0V. For DAC, VDDIN needs to be greater than 2.4V. Figure 5-2.
  • Page 21: Active Mode

    SAM4S Series [Preliminary] Figure 5-3. Backup Battery ADC, DAC, Analog Comparator Supply (2.0V-3.6V) VDDIO Backup Transceivers. Battery ADC, DAC Analog Comp. VDDIN Main Supply VDDOUT Voltage 3.3V Regulator VDDCORE ON/OFF VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode.
  • Page 22 Entering Backup mode: • Set the SLEEPDEEP bit of Cortex_M4 to 1 • Set the VROFF bit of SUPC_CR to 1 Exit from Backup mode happens if one of the following enable wake up events occurs: • WKUPEN0-15 pins (level transition, configurable debouncing) •...
  • Page 23 SAM4S Series [Preliminary] 5.5.3 Sleep Mode The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application dependent. This mode is entered via Wait for Interrupt (WFI) instructions with LPM = 0 in PMC_FSMR.
  • Page 24: Wake-Up Sources

    Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4.
  • Page 25: Fast Startup

    SAM4S Series [Preliminary] Fast Startup The SAM4S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT).
  • Page 26: Input/Output Lines

    6. Input/Output Lines The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed peripheral.
  • Page 27 SAM4S Series [Preliminary] Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function Constraints for bit number after reset Other function normal start Configuration ERASE PB12 Low Level at startup PB10 In Matrix User Interface Registers PB11 (Refer to the System I/O TCK/SWCLK Configuration Register in the “Bus TMS/SWDIO...
  • Page 28: Test Pin

    Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section.
  • Page 29: Product Mapping

    SAM4S Series [Preliminary] 7. Product Mapping Figure 7-1. SAM4S Product Mapping Address memory space Peripherals Code 0x40000000 0x00000000 0x00000000 HSMCI Boot Memory Code 0x40004000 0x00400000 1 MByte 1 MByte Internal Flash 0x20000000 bit band bit band 0x40008000 0x00800000 0x20100000 regiion regiion SRAM Internal ROM...
  • Page 30: Memories

    8. Memories Embedded Memories 8.1.1 Internal SRAM The SAM4SD32 device (2x1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM. The SAM4SD16 device (2x512KBytes)embeds a total of 160-Kbytes high-speed SRAM. The SAM4SA16 device (1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM. The SAM4S16 device (1024 Kbytes) embeds a total of 128-Kbytes high-speed SRAM.
  • Page 31 SAM4S Series [Preliminary] Figure 8-1. Global Flash Organization Sector size Sector name 8 KBytes Small Sector 0 8 KBytes Small Sector 1 Sector 0 Larger Sector 48 KBytes 64 KBytes Sector 1 64 KBytes Sector n Each Sector is organized in pages of 512 Bytes. For sector 0: •...
  • Page 32 Figure 8-2. Flash Sector Organization A sector size is 64 KBytes 16 pages of 512 Bytes Smaller sector 0 16 pages of 512 Bytes Smaller sector 1 Sector 0 96 pages of 512 Bytes Larger sector Sector 1 128 pages of 512 Bytes Sector n 128 pages of 512 Bytes Flash size varies by product:...
  • Page 33 SAM4S Series [Preliminary] Refer to Figure 8-3, "Flash Size" below for the organization of the Flash following its size. Figure 8-3. Flash Size Flash 1 MBytes Flash 512 KBytes Flash 256 KBytes 2 * 8 KBytes 2 * 8 KBytes 2 * 8 KBytes 1 * 48 KBytes 1 * 48 KBytes...
  • Page 34 8.1.3.4 Lock Regions Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 8-1. Lock Bit Number Product Number of Lock Bits Lock Region Size...
  • Page 35 SAM4S Series [Preliminary] 8.1.3.9 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
  • Page 36: External Memories

    Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default. External Memories The SAM4S features one External Bus Interface to provide an interface to a wide range of exter- nal memories and to any parallel peripheral.
  • Page 37: Vddin

    SAM4S Series [Preliminary] Figure 9-1. System Controller Block Diagram VDDIO VDDOUT vr_on Software Controlled vr_mode VDDIN Voltage Regulator VDDIO Supply Zero-Power Controller Power-on Reset PIOA/B/C PIOx Input/Output Buffers Supply Monitor (Backup) Analog WKUP0 - WKUP15 Comparator General Purpose ADC Analog Backup Registers Circuitry ADVREF...
  • Page 38: System Controller And Peripheral Mapping

    System Controller and Peripheral Mapping Refer to Figure 7-1, "SAM4S Product Mapping". All the peripherals are in the bit band region and are mapped in the bit band alias region. Power-on-Reset, Brownout and Supply Monitor The SAM4S embeds three features to monitor, warn and/or reset the chip: •...
  • Page 39: Peripherals

    SAM4S Series [Preliminary] 10. Peripherals 10.1 Peripheral Identifiers Table 10-1 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 10-1.
  • Page 40 Table 10-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt Clock Control Instance Description Pulse Width Modulation CRCCU CRC Calculation Unit Analog Comparator USB Device Port 10.2 Peripheral Signal Multiplexing on I/O Lines The SAM4S features 2 PIO controllers on 64-pin versions (PIOA and PIOB) or 3 PIO controllers on the 100-pin version (PIOA, PIOB and PIOC), that multiplex the I/O lines of the peripheral set.
  • Page 41 SAM4S Series [Preliminary] 10.2.1 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PWMH0 TIOA0 WKUP0 PWMH1 TIOB0 WKUP1 PWMH2 SCK0 DATRG WKUP2 TWD0 NPCS3 TWCK0 TCLK0...
  • Page 42 10.2.2 PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B (PIOB) Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PWMH0 AD4/RTCOUT0 PWMH1 AD5/RTCOUT1 URXD1 NPCS2 AD6/WKUP12 UTXD1 PCK2 TWD1 PWMH2 TWCK1 PWML0 WKUP13 TDO/TRACESWO TMS/SWDIO TCK/SWCLK XOUT...
  • Page 43 SAM4S Series [Preliminary] 10.2.3 PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C (PIOC) Extra System I/O Line Peripheral A Peripheral B Peripheral C Function Function Comments PWML0 100 pin version PWML1 100 pin version PWML2 100 pin version PWML3 100 pin version NPCS1...
  • Page 44 SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 45 SAM4S Series [Preliminary] 11. ARM Cortex-M4 11.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcon- troller market. It offers significant benefits to developers, including outstanding processing performance combined with fast interrupt handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core, system and memories, ultra-low power consumption with integrated sleep modes, and platform security robustness,...
  • Page 46 11.1.2 Integrated Configurable Debug The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit.
  • Page 47 SAM4S Series [Preliminary] 11.3 Block Diagram Figure 11-1. Typical Cortex-M4 Implementation Cortex-M4 Processor NVIC Processor Core Debug Serial Memory Access Wire Protection Unit Port Viewer Flash Data Patch Watchpoints Bus Matrix Code SRAM and Interface Peripheral Interface 11100B–ATARM–31-Jul-12...
  • Page 48 11.4 Cortex-M4 Models 11.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core reg- ister descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 11.4.1.1 Processor Modes And Privilege Levels for Software Execution The processor modes are: •...
  • Page 49 SAM4S Series [Preliminary] The options for processor operations are: Table 11-1. Summary of processor mode, execution privilege level, and stack use options Processor Used to Privilege Level for Mode Execute Software Execution Stack Used Main stack or Thread Applications Privileged or unprivileged process stack Handler Exception handlers...
  • Page 50 Table 11-2. Core Processor Registers Required Register Name Access Privilege Reset Link Register Read-write Either 0xFFFFFFFF Program Counter Read-write Either See description Program Status Register Read-write Privileged 0x01000000 Application Program Status Register APSR Read-write Either 0x00000000 Interrupt Program Status Register IPSR Read-only Privileged...
  • Page 51 SAM4S Series [Preliminary] 11.4.1.8 Program Status Register Name: Access: Read-write Reset: 0x000000000 ICI/IT – ICI/IT – ISR_NUMBER ISR_NUMBER The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR.
  • Page 52 11.4.1.9 Application Program Status Register Name: APSR Access: Read-write Reset: 0x000000000 – – GE[3:0] – – The APSR contains the current state of the condition flags from previous instruction executions. • N: Negative Flag 0: operation result was positive, zero, greater than, or equal 1: operation result was negative or less than.
  • Page 53 SAM4S Series [Preliminary] 11.4.1.10 Interrupt Program Status Register Name: IPSR Access: Read-write Reset: 0x000000000 – – – ISR_NUMBER ISR_NUMBER The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). • ISR_NUMBER: Number of the Current Exception 0 = Thread mode 1 = Reserved 2 = NMI...
  • Page 54 11.4.1.11 Execution Program Status Register Name: EPSR Access: Read-write Reset: 0x00000000 – ICI/IT – ICI/IT – – The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interrupt- ible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero.
  • Page 55 SAM4S Series [Preliminary] 11.4.1.12 Exception Mask Registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruc- tion to change the value of PRIMASK or FAULTMASK.
  • Page 56 11.4.1.14 Fault Mask Register Name: FAULTMASK Access: Read-write Reset: 0x00000000 – – – – FAULTMASK The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). • FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
  • Page 57 SAM4S Series [Preliminary] 11.4.1.15 Base Priority Mask Register Name: BASEPRI Access: Read-write Reset: 0x00000000 – – – BASEPRI The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. •...
  • Page 58 11.4.1.16 CONTROL Register Name: CONTROL Access: Read-write Reset: 0x00000000 – – – – – SPSEL nPRIV The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. • SPSEL: Active Stack Pointer Defines the current stack: 0: MSP is the current stack pointer.
  • Page 59 SAM4S Series [Preliminary] 11.4.1.17 Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset.
  • Page 60 11.4.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. Figure 11-3. Memory Map 0xFFFFFFFF Vendor-specific 511MB memory 0xE0100000...
  • Page 61 SAM4S Series [Preliminary] Memory Types • Normal The processor can re-order transactions for efficiency, or perform speculative reads. • Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. • Strongly-ordered The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly- ordered memory.
  • Page 62 Where: Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is, A1 is always observed before A2. 11.4.2.3 Behavior of Memory Accesses The behavior of accesses to each region in the memory map is: Table 11-4.
  • Page 63 SAM4S Series [Preliminary] Table 11-5. Memory Region Shareability Policies (Continued) Address Range Memory Region Memory Type Shareability 0x60000000- WBWA 0x7FFFFFFF External RAM Normal 0x80000000- 0x9FFFFFFF 0xA0000000- Shareable 0xBFFFFFFF External device Device 0xC0000000- Non-shareable 0xDFFFFFFF 0xE0000000- Private Peripheral Strongly- ordered Shareable 0xE00FFFFF 0xE0100000- Vendor-specific...
  • Page 64 MPU Programming Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU con- figuration is used by subsequent instructions. 11.4.2.5 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
  • Page 65 SAM4S Series [Preliminary] • Bit_band_base is the starting address of the alias region. • Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. • Bit_number is the bit position, 0-7, of the targeted bit. Figure 11-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region:...
  • Page 66 Directly Accessing a Bit-band Region “Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 11.4.2.6 Memory Endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero.
  • Page 67 SAM4S Series [Preliminary] To perform an exclusive read-modify-write of a memory location, the software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location 4.
  • Page 68 Table 11-8. CMSIS Functions for Exclusive Access Instructions (Continued) Instruction CMSIS Function STREX uint32_t __STREXW (uint32_t value, uint32_t *addr) STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr) STREXB uint32_t __STREXB (uint8_t value, uint8_t *addr) CLREX void __CLREX (void) The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic function.
  • Page 69 SAM4S Series [Preliminary] 11.4.3 Exception Model This section describes the exception model. 11.4.3.1 Exception States Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the correspond- ing interrupt to pending.
  • Page 70 Memory Management Fault (MemManage) A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.
  • Page 71 SAM4S Series [Preliminary] Table 11-9. Properties of the Different Exception Types (Continued) Exception Vector Address Number Irq Number Exception Type Priority or Offset Activation Memory Configurable 0x00000010 Synchronous management fault Synchronous when Bus fault Configurable 0x00000014 precise, asynchronous when imprecise Usage fault Configurable 0x00000018...
  • Page 72 11.4.3.4 Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 11-5 shows the order of the excep- tion vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.
  • Page 73 SAM4S Series [Preliminary] Note: Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0].
  • Page 74 This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initi- ates the vector fetch for that exception.
  • Page 75 SAM4S Series [Preliminary] Figure 11-6. Exception Stack Frame Pre-IRQ top of stack {aligner} FPSCR Pre-IRQ top of stack {aligner} Decreasing xPSR xPSR memory address IRQ top of stack IRQ top of stack Exception frame with Exception frame without floating-point storage floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
  • Page 76 Exception Return An Exception return occurs when the processor is in Handler mode and executes one of the fol- lowing instructions to load the EXC_RETURN value into the PC: • an instruction that loads the PC • an instruction with the PC as the destination. •...
  • Page 77 SAM4S Series [Preliminary] Table 11-11. Faults (Continued) Fault Handler Bit Name Fault Status Register MPU or default memory map mismatch: on instruction access IACCVIOL Memory on data access DACCVIOL management “MMFSR: Memory Management Fault during exception stacking MSTKERR fault Status Subregister” during exception unstacking MUNSKERR during lazy floating-point state preservation...
  • Page 78 • A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed.
  • Page 79 SAM4S Series [Preliminary] 11.5 Power Management The Cortex-M4 processor sleep modes reduce the power consumption: • Sleep mode stops the processor clock • Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Regis- ter”...
  • Page 80 11.5.2.2 Wakeup from WFE The processor wakes up if: • it detects an exception with sufficient priority to cause an exception entry • it detects an external event signal. See “External Event Input” • in a multiprocessor system, another processor in the system executes an SEV instruction. In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry.
  • Page 81 SAM4S Series [Preliminary] 11.6 Cortex-M4 Instruction Set 11.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 11-13 lists the sup- ported instructions. • angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands •...
  • Page 82 Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags If-Then condition block Rn{!}, reglist Load Multiple registers, increment after LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after Rt, [Rn, #offset] Load Register with word LDRB, LDRBT Rt, [Rn, #offset]...
  • Page 83 SAM4S Series [Preliminary] Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags QDSUB {Rd,} Rn, Rm Saturating double and Subtract QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange QSUB {Rd,} Rn, Rm Saturating Subtract QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 QSUB8 {Rd,} Rn, Rm...
  • Page 84 Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags SMULBB, SMULBT {Rd,} Rn, Rm Signed Multiply (halfwords) SMULTB, SMULTT SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract...
  • Page 85 SAM4S Series [Preliminary] Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract UDIV {Rd,} Rn, Rm Unsigned Divide UMAAL RdLo, RdHi, Rn, Rm...
  • Page 86 The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 11-14. CMSIS Functions to Generate some Cortex-M4 Instructions Instruction CMSIS Function CPSIE I void __enable_irq(void) CPSID I void __disable_irq(void) CPSIE F void __enable_fault_irq(void) CPSID F void __disable_fault_irq(void) void __ISB(void)
  • Page 87 SAM4S Series [Preliminary] 11.6.3 Instruction Descriptions 11.6.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible, can either be a register or a constant.
  • Page 88 Register with Optional Shift Specify an Operand2 register in the form: Rm {, shift} where: is the register holding the data for the second operand. shift is an optional shift to be applied to Rm. It can be one of: arithmetic shift right n bits, 1 ≤...
  • Page 89 SAM4S Series [Preliminary] Figure 11-7. ASR #3 Carry Flag 5 4 3 2 1 Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. Figure 11-8.
  • Page 90 Figure 11-9. LSL #3 5 4 3 2 1 Carry Flag Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register into the left-hand n bits of the result.
  • Page 91 SAM4S Series [Preliminary] 11.6.3.5 Address Alignment An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. The Cortex-M4 processor supports unaligned access only for the following instructions: •...
  • Page 92 • does not execute • does not write any value to its destination register • does not affect any of the flags • does not generate any exception. Conditional instructions, except for conditional branches, must be inside an If-Then instruction block.
  • Page 93 SAM4S Series [Preliminary] A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code. Table 11-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 11-16.
  • Page 94 the user can force a specific instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding. If the user specifies an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error.
  • Page 95 SAM4S Series [Preliminary] 11.6.4.1 Load PC-relative address. Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional Execution” is the destination register. label is a PC-relative expression. See “PC-relative Expressions” Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register.
  • Page 96 11.6.4.2 LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. Syntax op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed op{type}{cond} Rt, [Rn], #offset ; post-indexed opD{cond} Rt, Rt2, [Rn {, #offset}] ;...
  • Page 97 SAM4S Series [Preliminary] Pre-indexed Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! Post-indexed Addressing...
  • Page 98 Condition Flags These instructions do not change the flags. Examples R8, [R10] ; Loads R8 from the address in R10. LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word ; 960 bytes above the address in R5, and ;...
  • Page 99 SAM4S Series [Preliminary] The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL. The value to load or store can be a byte, halfword, or word.
  • Page 100 cond is an optional condition code, see “Conditional Execution” is the register to load or store. is the register on which the memory address is based. offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn. Operation These load and store instructions perform the same function as the memory access instructions with immediate offset, see...
  • Page 101 SAM4S Series [Preliminary] is the second register to load or store. label is a PC-relative expression. See “PC-relative Expressions” Operation LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC. The value to load or store can be a byte, halfword, or word.
  • Page 102 11.6.4.6 LDM and STM Load and Store Multiple registers. Syntax op{addr_mode}{cond} Rn{!}, reglist where: is one of: Load Multiple registers. Store Multiple registers. addr_mode is any one of the following: Increment address After each access. This is the default. Decrement address Before each access. cond is an optional condition code, see “Conditional Execution”...
  • Page 103 SAM4S Series [Preliminary] The accesses happen in order of decreasing register numbers, with the highest numbered regis- ter using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form.
  • Page 104 11.6.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional Execution” reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges.
  • Page 105 SAM4S Series [Preliminary] 11.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional Execution”...
  • Page 106 Condition Flags These instructions do not change the flags. Examples R1, #0x1 ; Initialize the ‘lock taken’ value LDREX R0, [LockAddr] ; Load the lock value R0, #0 ; Is the lock free? ; IT instruction for STREXEQ and CMPEQ STREXEQ R0, R1, [LockAddr] ;...
  • Page 107 SAM4S Series [Preliminary] 11.6.5 General Data Processing Instructions The table below shows the data processing instructions: Table 11-20. Data Processing Instructions Mnemonic Description Add with Carry ADDW Logical AND Arithmetic Shift Right Bit Clear Count leading zeros Compare Negative Compare Exclusive OR Logical Shift Left Logical Shift Right...
  • Page 108 Table 11-20. Data Processing Instructions (Continued) Mnemonic Description SHSUB16 Signed Halving Subtract 16 SHSUB8 Signed Halving Subtract 8 SSUB16 Signed Subtract 16 SSUB8 Signed Subtract 8 Subtract SUBW Subtract Test Equivalence Test UADD16 Unsigned Add 16 UADD8 Unsigned Add 8 UASX Unsigned Add and Subtract with Exchange USAX...
  • Page 109 SAM4S Series [Preliminary] 11.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: is one of: Add. Add with Carry.
  • Page 110 – if the instruction is conditional, it must be the last instruction in the IT block • with the exception of the instruction, can be PC only in , and ADD{cond} PC, PC, Rm only with the additional restrictions: – the user must not specify the S suffix –...
  • Page 111 SAM4S Series [Preliminary] 11.6.5.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where: is one of: logical AND. logical OR, or bit set. logical Exclusive OR. logical AND NOT, or bit clear. logical OR NOT.
  • Page 112 11.6.5.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: is one of: Arithmetic Shift Right. Logical Shift Left.
  • Page 113 SAM4S Series [Preliminary] Examples R7, R8, #9 ; Arithmetic shift right by 9 bits LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update R4, R5, #6 ; Logical shift right by 6 bits R4, R5, R6 ;...
  • Page 114 11.6.5.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional Execution” is the register holding the first operand. is a flexible second operand. See “Flexible Second Operand” for details of the Operand2 options.
  • Page 115 SAM4S Series [Preliminary] 11.6.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: is an optional suffix. If is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution”...
  • Page 116 Though it is possible to use as a branch instruction, ARM strongly recommends the use of a instruction to branch for software portability to the ARM instruction set. Condition Flags is specified, these instructions: • update the N and Z flags according to the result •...
  • Page 117 SAM4S Series [Preliminary] 11.6.5.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn where: is any of: Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word.
  • Page 118 11.6.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: SADD16 Performs two 16-bit signed integer additions. Performs four 8-bit signed integer additions. SADD8 cond is an optional condition code, see “Conditional Execution”...
  • Page 119 SAM4S Series [Preliminary] 11.6.5.10 SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: Signed Halving Add 16 SHADD16 SHADD8 Signed Halving Add 8 cond is an optional condition code, see “Conditional Execution”...
  • Page 120 11.6.5.11 SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: is any of: Add and Subtract with Exchange and Halving. SHASX SHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution”...
  • Page 121 SAM4S Series [Preliminary] ; Adds top halfword of R5 to bottom halfword of R3 and ; writes halved result to bottom halfword of R0. 11.6.5.12 SHSUB16 and SHSUB8 Signed Halving Subtract 16 and Signed Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: Signed Halving Subtract 16...
  • Page 122 11.6.5.13 SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: SSUB16 Performs two 16-bit signed integer subtractions. Performs four 8-bit signed integer subtractions. SSUB8 cond is an optional condition code, see “Conditional Execution”...
  • Page 123 SAM4S Series [Preliminary] 11.6.5.14 SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: is any of: Signed Add and Subtract with Exchange. SASX SSAX Signed Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution”...
  • Page 124 11.6.5.15 TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional Execution” is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand”...
  • Page 125 SAM4S Series [Preliminary] 11.6.5.16 UADD16 and UADD8 Unsigned Add 16 and Unsigned Add 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: Performs two 16-bit unsigned integer additions. UADD16 UADD8 Performs four 8-bit unsigned integer additions. cond is an optional condition code, see “Conditional Execution”...
  • Page 126 11.6.5.17 UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: is one of: UASX Add and Subtract with Exchange. Subtract and Add with Exchange. USAX cond is an optional condition code, see “Conditional Execution”...
  • Page 127 SAM4S Series [Preliminary] 11.6.5.18 UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: Unsigned Halving Add 16. UHADD16 UHADD8 Unsigned Halving Add 8. cond is an optional condition code, see “Conditional Execution”...
  • Page 128 where: is one of: UHASX Add and Subtract with Exchange and Halving. Subtract and Add with Exchange and Halving. UHSAX cond is an optional condition code, see “Conditional Execution” is the destination register. Rn, Rm are registers holding the first and second operands. Operation instruction: UHASX...
  • Page 129 SAM4S Series [Preliminary] 11.6.5.20 UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: Performs two unsigned 16-bit integer additions, halves the results, and writes UHSUB16 the results to the destination register. Performs four unsigned 8-bit integer additions, halves the results, and writes UHSUB8 the results to the destination register.
  • Page 130 11.6.5.21 Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. Syntax SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm> where: <c>, <q> is a standard assembler syntax fields. <Rd>...
  • Page 131 SAM4S Series [Preliminary] 11.6.5.22 USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” is the destination register. is the first operand register. is the second operand register. Operation instruction: USAD8 1.
  • Page 132 11.6.5.23 USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond is an optional condition code, see “Conditional Execution” is the destination register. is the first operand register. is the second operand register. is the register that contains the accumulation value. Operation instruction: USADA8...
  • Page 133 SAM4S Series [Preliminary] 11.6.5.24 USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: is any of: Unsigned Subtract 16. USUB16 USUB8 Unsigned Subtract 8. cond is an optional condition code, see “Conditional Execution” is the destination register. is the first operand register.
  • Page 134 11.6.6 Multiply and Divide Instructions The table below shows the multiply and divide instructions: Table 11-21. Multiply and Divide Instructions Mnemonic Description Multiply with Accumulate, 32-bit result Multiply and Subtract, 32-bit result Multiply, 32-bit result SDIV Signed Divide SMLA[B,T] Signed Multiply Accumulate (halfwords) SMLAD, SMLADX Signed Multiply Accumulate Dual SMLAL...
  • Page 135 SAM4S Series [Preliminary] 11.6.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro- ducing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ;...
  • Page 136 11.6.6.2 UMULL, UMAAL, UMLAL Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: is one of: Unsigned Long Multiply. UMULL UMAAL Unsigned Long Multiply with Accumulate Accumulate. Unsigned Long Multiply, with Accumulate. UMLAL cond is an optional condition code, see...
  • Page 137 SAM4S Series [Preliminary] 11.6.6.3 SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra where is one of: SMLA Signed Multiply Accumulate Long (halfwords) specifies which half of the source registers are used as the first and second multiply operand.
  • Page 138 Examples SMLABB R5, R6, R4, R1 ; Multiplies bottom halfwords of R6 and R4, adds ; R1 and writes to R5 SMLATB R5, R6, R4, R1 ; Multiplies top halfword of R6 with bottom halfword ; of R4, adds R1 and writes to R5 SMLATT R5, R6, R4, R1 ;...
  • Page 139 SAM4S Series [Preliminary] 11.6.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra where: is one of: SMLAD Signed Multiply Accumulate Dual SMLADX Signed Multiply Accumulate Dual Reverse X specifies which halfword of the source register is used as the multiply operand. is omitted, the multiplications are bottom ×...
  • Page 140 11.6.6.5 SMLAL and SMLALD Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual. Syntax op{cond} RdLo, RdHi, Rn, Rm op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm where: is one of: SMLAL Signed Multiply Accumulate Long SMLAL Signed Multiply Accumulate Long (halfwords, X and Y) X and Y specify which halfword of the source registers are used as the first...
  • Page 141 SAM4S Series [Preliminary] • Add the two multiplication results to the signed 64-bit value in to create the RdLo RdHi resulting 64-bit product. • Write the 64-bit product in RdLo RdHi Restrictions In these instructions: • do not use SP and do not use PC. •...
  • Page 142 Operation instruction interprets the values from the first and second operands as four signed SMLSD halfwords. This instruction: • Optionally rotates the halfwords of the second operand. • Performs two signed 16 × 16-bit halfword multiplications. • Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
  • Page 143 SAM4S Series [Preliminary] 11.6.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where: is one of: SMMLA Signed Most Significant Word Multiply Accumulate. SMMLS Signed Most Significant Word Multiply Subtract. is a rounding error flag.
  • Page 144 Examples SMMLA R0, R4, R5, R6 ; Multiplies R4 and R5, extracts top 32 bits, ; adds R6, truncates and writes to R0 SMMLAR R6, R2, R1, R4 ; Multiplies R2 and R1, extracts top 32 bits, ; adds R4, rounds and writes to R6 SMMLSR R3, R6, R2, R7 ;...
  • Page 145 SAM4S Series [Preliminary] 11.6.6.9 SMUAD and SMUSD Signed Dual Multiply Add and Signed Dual Multiply Subtract Syntax op{X}{cond} Rd, Rn, Rm where: is one of: Signed Dual Multiply Add. SMUAD SMUADX Signed Dual Multiply Add Reversed. SMUSD Signed Dual Multiply Subtract. SMUSDX Signed Dual Multiply Subtract Reversed.
  • Page 146 Examples SMUAD R0, R4, R5 ; Multiplies bottom halfword of R4 with the bottom ; halfword of R5, adds multiplication of top halfword ; of R4 with top halfword of R5, writes to R0 SMUADX R3, R7, R4 ; Multiplies bottom halfword of R7 with top halfword ;...
  • Page 147 SAM4S Series [Preliminary] • Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand. • Writes the signed most significant 32 bits of the 48-bit result in the destination register. Restrictions In these instructions: •...
  • Page 148 11.6.6.11 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro- ducing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: is one of: Unsigned Long Multiply. UMULL UMLAL Unsigned Long Multiply, with Accumulate. Signed Long Multiply.
  • Page 149 SAM4S Series [Preliminary] 11.6.6.12 SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” is omitted, the destination register is is the destination register. If is the register holding the value to be divided.
  • Page 150 11.6.7 Saturating Instructions The table below shows the saturating instructions: Table 11-22. Saturating Instructions Mnemonic Description SSAT Signed Saturate SSAT16 Signed Saturate Halfword USAT Unsigned Saturate USAT16 Unsigned Saturate Halfword QADD Saturating Add QSUB Saturating Subtract QSUB16 Saturating Subtract 16 QASX Saturating Add and Subtract with Exchange QSAX...
  • Page 151 SAM4S Series [Preliminary] 11.6.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: is one of: Saturates a signed value to a signed range. SSAT USAT Saturates a signed value to an unsigned range.
  • Page 152 11.6.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: is one of: SSAT16 Saturates a signed halfword value to a signed range. Saturates a signed halfword value to an unsigned range. USAT16 cond is an optional condition code, see...
  • Page 153 SAM4S Series [Preliminary] 11.6.7.3 QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: is one of: Saturating 32-bit add. QADD Saturating four 8-bit integer additions. QADD8 Saturating two 16-bit integer additions. QADD16 Saturating 32-bit subtraction.
  • Page 154 QSUB16 R4, R2, R3 ; Subtracts halfwords of R3 from corresponding halfword ; of R2, saturates to 16 bits, writes to corresponding ; halfword of R4 QSUB8 R4, R2, R5 ; Subtracts bytes of R5 from the corresponding byte in ;...
  • Page 155 SAM4S Series [Preliminary] Examples QASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2, ; saturates to 16 bits, writes to top halfword of R7 ; Subtracts top highword of R2 from bottom halfword of ;...
  • Page 156 Examples QDADD R7, R4, R2 ; Doubles and saturates R4 to 32 bits, adds R2, ; saturates to 32 bits, writes to R7 QDSUB R0, R3, R5 ; Subtracts R3 doubled and saturated to 32 bits ; from R5, saturates to 32 bits, writes to R0. 11.6.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange,...
  • Page 157 SAM4S Series [Preliminary] Examples UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2, ; saturates to 16 bits, writes to top halfword of R7 ; Subtracts top halfword of R2 from bottom halfword of R4 ;...
  • Page 158 • Subtracts the respective bytes of the second operand from the respective bytes of the first operand. • Saturates the results of the differences for each byte in the destination register to the unsigned range 0 £ x £ 2 -1, where x is 8.
  • Page 159 SAM4S Series [Preliminary] 11.6.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} where: is one of: Pack Halfword, bottom and top with shift. PKHBT Pack Halfword, top and bottom with shift. PKHTB cond is an optional condition code, see...
  • Page 160 11.6.8.2 SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} where: is one of: Sign extends an 8-bit value to a 32-bit value. SXTB Sign extends a 16-bit value to a 32-bit value. SXTH SXTB16 Sign extends two 8-bit values to two 16-bit values.
  • Page 161 SAM4S Series [Preliminary] 11.6.8.3 SXTA and UXTA Signed and Unsigned Extend and Add Syntax op{cond} {Rd,} Rn, Rm {, ROR #n} op{cond} {Rd,} Rn, Rm {, ROR #n} where: is one of: Sign extends an 8-bit value to a 32-bit value and add. SXTAB Sign extends a 16-bit value to a 32-bit value and add.
  • Page 162 Examples SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom ; halfword, sign extends to 32 bits, adds R8,and ; writes to R4 UXTAB R3, R4, R10 ; Extracts bottom byte of R10 and zero extends to ;...
  • Page 163 SAM4S Series [Preliminary] Condition Flags These instructions do not affect the flags. Examples R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with ;...
  • Page 164 11.6.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: Extends an 8-bit value to a 32-bit value. Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional Execution”...
  • Page 165 SAM4S Series [Preliminary] 11.6.10 Branch and Control Instructions The table below shows the branch and control instructions: Table 11-25. Branch and Control Instructions Mnemonic Description Branch Branch with Link Branch indirect with Link Branch indirect CBNZ Compare and Branch if Non Zero Compare and Branch if Zero If-Then Table Branch Byte...
  • Page 166 The table below shows the ranges for the various branch instructions. Table 11-26. Branch Ranges Instruction Branch Range − 16 MB to +16 MB B label − 1 MB to +1 MB (outside IT block) Bcond label − 16 MB to +16 MB (inside IT block) Bcond label −...
  • Page 167 SAM4S Series [Preliminary] 11.6.10.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: is the register holding the operand. label is the branch destination. Operation Use the instructions to avoid changing the condition code flags and to reduce the CBNZ number of instructions.
  • Page 168 11.6.10.3 If-Then condition instruction. Syntax IT{x{y{z}}} cond where: specifies the condition switch for the second instruction in the IT block. specifies the condition switch for the third instruction in the IT block. specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block.
  • Page 169 SAM4S Series [Preliminary] – MOV PC, Rm – – any , or instruction that writes to the PC – • do not branch to any instruction inside an IT block, except when returning from an exception handler • all conditional instructions except must be inside an IT block.
  • Page 170 11.6.10.4 TBB and TBH Table Branch Byte and Table Branch Halfword. Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: is the register containing the address of the table of branch lengths. is PC, then the address of the table is the address of the byte immediately following the instruction.
  • Page 171 SAM4S Series [Preliminary] ((CaseC - BranchTable_H)/2) ; CaseC offset calculation CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows 11.6.11 Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions: Table 11-27. Miscellaneous Instructions Mnemonic Description BKPT...
  • Page 172 11.6.11.1 BKPT Breakpoint. Syntax BKPT #imm where: is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor.
  • Page 173 SAM4S Series [Preliminary] Restrictions The restrictions are: • use CPS only from privileged software, it has no effect if used in unprivileged software • CPS cannot be conditional and so must not be used inside an IT block. Condition Flags This instruction does not change the condition flags.
  • Page 174 11.6.11.4 Data Synchronization Barrier. Syntax DSB{cond} where: cond is an optional condition code, see “Conditional Execution” Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.
  • Page 175 SAM4S Series [Preliminary] 11.6.11.6 Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional Execution” is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
  • Page 176 11.6.11.7 Move the contents of a general-purpose register into the specified special register. Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see “Conditional Execution” is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
  • Page 177 SAM4S Series [Preliminary] 11.6.11.8 No Operation. Syntax NOP{cond} where: cond is an optional condition code, see “Conditional Execution” Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
  • Page 178 11.6.11.10 Supervisor Call. Syntax SVC{cond} #imm where: cond is an optional condition code, see “Conditional Execution” is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested.
  • Page 179 SAM4S Series [Preliminary] 11.6.11.11 Wait For Event. Syntax WFE{cond} where: cond is an optional condition code, see “Conditional Execution” Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: •...
  • Page 180 11.7 Cortex-M4 Core Peripherals 11.7.1 Peripherals • Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. See Section 11.8 ”Nested Vectored Interrupt Controller (NVIC)” • System Control Block (SCB) The System Control Block (SCB) is the programmers model interface to the processor.
  • Page 181 SAM4S Series [Preliminary] 11.8 Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports: • 1 to 35 interrupts. • A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
  • Page 182 11.8.2 NVIC Design Hints and Tips Ensure that the software uses correctly aligned register accesses. The processor does not sup- port unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
  • Page 183 SAM4S Series [Preliminary] • the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n. The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis- ters.
  • Page 184 11.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface Table 11-30. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register Name Access Reset 0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read-write 0x00000000 0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read-write 0x00000000 0XE000E180 Interrupt Clear-enable Register0 NVIC_ICER0 Read-write 0x00000000...
  • Page 185 SAM4S Series [Preliminary] 11.8.3.1 Interrupt Set-enable Registers Name: NVIC_ISERx [x=0..7] Access: Read-write Reset: 0x000000000 SETENA SETENA SETENA SETENA These registers enable interrupts, and show which interrupts are enabled. • SETENA: Interrupt Set-enable Write: 0: No effect. 1: Enables the interrupt. Read: 0: Interrupt disabled.
  • Page 186 11.8.3.2 Interrupt Clear-enable Registers Name: NVIC_ICERx [x=0..7] Access: Read-write Reset: 0x000000000 CLRENA CLRENA CLRENA CLRENA These registers disable interrupts, and show which interrupts are enabled. • CLRENA: Interrupt Set-enable Write: 0: No effect. 1: Disables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled.
  • Page 187 SAM4S Series [Preliminary] 11.8.3.3 Interrupt Set-pending Registers Name: NVIC_ISPRx [x=0..7] Access: Read-write Reset: 0x000000000 SETPEND SETPEND SETPEND SETPEND These registers force interrupts into the pending state, and show which interrupts are pending. • SETPEND: Interrupt Set-pending Write: 0: No effect. 1: Changes the interrupt state to pending.
  • Page 188 11.8.3.4 Interrupt Clear-pending Registers Name: NVIC_ICPRx [x=0..7] Access: Read-write Reset: 0x000000000 CLRPEND CLRPEND CLRPEND CLRPEND These registers remove the pending state from interrupts, and show which interrupts are pending. • CLRPEND: Interrupt Clear-pending Write: 0: No effect. 1: removes the pending state from an interrupt. Read: 0: Interrupt is not pending.
  • Page 189 SAM4S Series [Preliminary] 11.8.3.5 Interrupt Active Bit Registers Name: NVIC_IABRx [x=0..7] Access: Read-write Reset: 0x000000000 ACTIVE ACTIVE ACTIVE ACTIVE These registers indicate which interrupts are active. • ACTIVE: Interrupt Active Flags 0: Interrupt is not active. 1: Interrupt is active. Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
  • Page 190 11.8.3.6 Interrupt Priority Registers Name: NVIC_IPRx [x=0..8] Access: Read-write Reset: 0x000000000 PRI3 PRI2 PRI1 PRI0 The NVIC_IPR0-NVIC_IPR8 registers provide a 4-bit priority field for each interrupt. These registers are byte-accessible. Each register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[34] •...
  • Page 191 SAM4S Series [Preliminary] 11.8.3.7 Software Trigger Interrupt Register Name: NVIC_STIR Access: Write-only Reset: 0x000000000 – – – – – – – – – – – – – – – – – – – – – – – INTID INTID Write to this register to generate an interrupt from software. •...
  • Page 192 11.9 System Control Block (SCB) The System Control Block (SCB) provides system implementation information, and system con- trol. This includes configuration, control, and reporting of the system exceptions. Ensure that the software uses aligned accesses of the correct size to access the system control block registers: •...
  • Page 193 SAM4S Series [Preliminary] 11.9.1 System Control Block (SCB) User Interface Table 11-31. System Control Block (SCB) Register Mapping Offset Register Name Access Reset 0xE000E008 Auxiliary Control Register SCB_ACTLR Read-write 0x00000000 0xE000ED00 CPUID Base Register SCB_CPUID Read-only 0x410FC240 0xE000ED04 Interrupt Control and State Register SCB_ICSR Read-write 0x00000000...
  • Page 194 11.9.1.1 Auxiliary Control Register Name: SCB_ACTLR Access: Read-write Reset: 0x000000000 – – – DISOOFP DISFPCA – DISFOLD DISDEFWBUF DISMCYCINT The SCB_ACTLR register provides disable bits for the following processor functions: • IT folding • write buffer use for accesses to the default memory map •...
  • Page 195 SAM4S Series [Preliminary] 11.9.1.2 CPUID Base Register Name: SCB_CPUID Access: Read-write Reset: 0x000000000 Implementer Variant Constant PartNo Revision PartNo The SCB_CPUID register contains the processor part number, version, and implementation information. • Implementer: Implementer code 0x41: ARM. • Variant: Variant number It is the r value in the rnpn product revision identifier: 0x0: Revision 0.
  • Page 196 11.9.1.3 Interrupt Control and State Register Name: SCB_ICSR Access: Read-write Reset: 0x000000000 NMIPENDSET – PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR – – ISRPENDING VECTPENDING VECTPENDING RETTOBASE – VECTACTIVE VECTACTIVE The SCB_ICSR register provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions.
  • Page 197 SAM4S Series [Preliminary] 1: PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending. • PENDSVCLR: PendSV Clear-pending Write: 0: no effect. 1: removes the pending state from the PendSV exception. •...
  • Page 198 Note: When the user writes to the SCB_ICSR register, the effect is unpredictable if: - writing 1 to the PENDSVSET bit and writing 1 to the PENDSVCLR bit - writing 1 to the PENDSTSET bit and writing 1 to the PENDSTCLR bit. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 199 SAM4S Series [Preliminary] 11.9.1.4 Vector Table Offset Register Name: SCB_VTOR Access: Read-write Reset: 0x000000000 TBLOFF TBLOFF TBLOFF TBLOFF – The SCB_VTOR register indicates the offset of the vector table base address from memory address 0x00000000. • TBLOFF: Vector Table Base Offset It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
  • Page 200 11.9.1.5 Application Interrupt and Reset Control Register Name: SCB_AIRCR Access: Read-write Reset: 0x000000000 VECTKEYSTAT/VECTKEY VECTKEYSTAT/VECTKEY ENDIANNESS – PRIGROUP VECTCLRACTI – SYSRESETREQ VECTRESET The SCB_AIRCR register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores the write.
  • Page 201 SAM4S Series [Preliminary] Interrupt Priority Level Value, PRI_N[7:0] Number of PRIGROUP Binary Point Group Priority bits Subpriority bits Group Priorities Subpriorities 0b101 bxx.yyyyyy [7:6] [5:0] 0b110 bx.yyyyyyy [6:0] 0b111 b.yyyyyyy None [7:0] Note: 1. In the PRI_n[7:0] field showing the binary point, x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field.
  • Page 202 11.9.1.6 System Control Register Name: SCB_SCR Access: Read-write Reset: 0x000000000 – – – – SEVONPEND – SLEEPDEEP SLEEPONEXIT – • SEVONPEND: Send Event on Pending bit 0: only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1: enabled events and all interrupts, including disabled interrupts, can wake up the processor.
  • Page 203 SAM4S Series [Preliminary] 11.9.1.7 Configuration and Control Register Name: SCB_CCR Access: Read-write Reset: 0x000000000 – – – STKALIGN BFHFNMIGN USERSETMPE NONBASETHR – DIV_0_TRP UNALIGN_TRP – DENA The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults esca- lated by FAULTMASK to ignore BusFaults.
  • Page 204 • UNALIGN_TRP: Unaligned Access Trap Enables unaligned access traps: 0: do not trap unaligned halfword and word accesses. 1: trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. •...
  • Page 205 SAM4S Series [Preliminary] 11.9.1.8 System Handler Priority Registers The SCB_SHPR1-SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable pri- ority. They are byte-accessible. The system fault handlers and the priority field and register for each handler are: Table 11-32.
  • Page 206 11.9.1.9 System Handler Priority Register 1 Name: SCB_SHPR1 Access: Read-write Reset: 0x000000000 – PRI_6 PRI_5 PRI_4 • PRI_6: Priority Priority of system handler 6, UsageFault. • PRI_5: Priority Priority of system handler 5, BusFault. • PRI_4: Priority Priority of system handler 4, MemManage. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 207 SAM4S Series [Preliminary] 11.9.1.10 System Handler Priority Register 2 Name: SCB_SHPR2 Access: Read-write Reset: 0x000000000 PRI_11 – – – • PRI_11: Priority Priority of system handler 11, SVCall. 11100B–ATARM–31-Jul-12...
  • Page 208 11.9.1.11 System Handler Priority Register 3 Name: SCB_SHPR3 Access: Read-write Reset: 0x000000000 PRI_15 PRI_14 – – • PRI_15: Priority Priority of system handler 15, SysTick exception. • PRI_14: Priority Priority of system handler 14, PendSV. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 209 SAM4S Series [Preliminary] 11.9.1.12 System Handler Control and State Register Name: SCB_SHCSR Access: Read-write Reset: 0x000000000 – – USGFAULTENA BUSFAULTENA MEMFAULTENA SVCALLPENDE BUSFAULTPEN MEMFAULTPEN USGFAULTPEN SYSTICKACT PENDSVACT – MONITORACT SVCALLAVCT – USGFAULTACT – BUSFAULTACT MEMFAULTACT The SHCSR register enables the system handlers, and indicates the pending status of the bus fault, memory management fault, and SVC exceptions;...
  • Page 210 • MEMFAULTPENDED: Memory Management Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • USGFAULTPENDED: Usage Fault Exception Pending Read: 0: The exception is not pending.
  • Page 211 SAM4S Series [Preliminary] • MEMFAULTACT: Memory Management Fault Exception Active 0: Memory management fault exception is not active. 1: Memory management fault exception is active. If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. The user can write to this register to change the pending or active status of system exceptions.
  • Page 212 11.9.1.13 Configurable Fault Status Register Name: SCB_CFSR Access: Read-write Reset: 0x000000000 – DIVBYZERO UNALIGNED – NOCP INVPC INVSTATE UNDEFINSTR BFRVALID – STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR MMARVALID – MLSPERR MSTKERR MUNSTKERR – DACCVIOL IACCVIOL • IACCVIOL: Instruction Access Violation flag This is part of “MMFSR: Memory Management Fault Status Subregister”...
  • Page 213 SAM4S Series [Preliminary] When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not written a fault address to SCB_MMFAR register. • MLSPERR: MemManage during Lazy State Preservation This is part of “MMFSR: Memory Management Fault Status Subregister”...
  • Page 214 • UNSTKERR: Bus Fault on Unstacking for a Return From Exception This is part of “BFSR: Bus Fault Status Subregister” 0: No unstacking fault. 1: Unstack for an exception return has caused one or more bus faults. This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present.
  • Page 215 SAM4S Series [Preliminary] • INVPC: Invalid PC Load Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN: 0: No invalid PC load usage fault. 1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value.
  • Page 216 11.9.1.14 Configurable Fault Status Register (Byte Access) Name: SCB_CFSR (BYTE) Access: Read-write Reset: 0x000000000 UFSR UFSR BFSR MMFSR • MMFSR: Memory Management Fault Status Subregister The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section 11.9.1.13.
  • Page 217 SAM4S Series [Preliminary] 11.9.1.15 Hard Fault Status Register Name: SCB_HFSR Access: Read-write Reset: 0x00000000 DEBUGEVT FORCED – – – – VECTTBL – The HFSR register gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
  • Page 218 11.9.1.16 MemManage Fault Address Register Name: SCB_MMFAR Access: Read-write Reset: 0x000000000 ADDRESS ADDRESS ADDRESS ADDRESS The MMFAR register contains the address of the location that generated a memory management fault. • ADDRESS When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated the memory management fault.
  • Page 219 SAM4S Series [Preliminary] 11.9.1.17 Bus Fault Address Register Name: SCB_BFAR Access: Read-write Reset: 0x000000000 ADDRESS ADDRESS ADDRESS ADDRESS The BFAR register contains the address of the location that generated a bus fault. • ADDRESS When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus fault.
  • Page 220 11.10 System Timer (SysTick) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging, the counter does not decrement.
  • Page 221 SAM4S Series [Preliminary] 11.10.1.1 SysTick Control and Status Name: SYST_CSR Access: Read-write Reset: 0x000000000 – – COUNTFLAG – CLKSOURCE TICKINT ENABLE The SysTick SYST_CSR register enables the SysTick features. • COUNTFLAG: Count Flag Returns 1 if the timer counted to 0 since the last time this was read. •...
  • Page 222 11.10.1.2 SysTick Reload Value Registers Name: SYST_RVR Access: Read-write Reset: 0x000000000 – RELOAD RELOAD RELOAD The SYST_RVR register specifies the start value to load into the SYST_CVR register. • RELOAD Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0. The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF.
  • Page 223 SAM4S Series [Preliminary] 11.10.1.3 SysTick Current Value Register Name: SYST_CVR Access: Read-write Reset: 0x000000000 – CURRENT CURRENT CURRENT The SysTick SYST_CVR register contains the current value of the SysTick counter. • CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
  • Page 224 11.10.1.4 SysTick Calibration Value Register Name: SYST_CALIB Access: Read-write Reset: 0x000000000 NOREF SKEW – TENMS TENMS TENMS The SysTick SYST_CSR register indicates the SysTick calibration properties. • NOREF: No Reference Clock It indicates whether the device provides a reference clock to the processor: 0: Reference clock provided.
  • Page 225 SAM4S Series [Preliminary] 11.11 Memory Protection Unit (MPU) The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: • independent attribute settings for each region •...
  • Page 226 11.11.1 MPU Access Permission Attributes This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault.
  • Page 227 SAM4S Series [Preliminary] Table 11-36. Cache Policy for Memory Attribute Encoding (Continued) Encoding, AA or BB Corresponding Cache Policy Write back, write and read allocate Write through, no write allocate Write back, no write allocate shows the AP encodings that define the access permissions for privileged and Table 11-37 unprivileged software.
  • Page 228 Disable a region before writing new region settings to the MPU, if the region being changed was previously enabled . For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ;...
  • Page 229 SAM4S Series [Preliminary] Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region Number, address, attribute, size and enable This can be done in two words for pre-packed information.
  • Page 230 Figure 11-12. SRD Use Region 2, with Offset from subregions base address 512KB 448KB 384KB 320KB 256KB Region 1 192KB 128KB Disabled subregion 64KB Disabled subregion Base address of both regions 11.11.1.7 MPU Design Hints And Tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access.
  • Page 231 SAM4S Series [Preliminary] 11.11.2 Memory Protection Unit (MPU) User Interface Table 11-39. Memory Protection Unit (MPU) Register Mapping Offset Register Name Access Reset 0xE000ED90 MPU Type Register MPU_TYPE Read-only 0x00000800 0xE000ED94 MPU Control Register MPU_CTRL Read-write 0x00000000 0xE000ED98 MPU Region Number Register MPU_RNR Read-write 0x00000000...
  • Page 232 11.11.2.1 MPU Type Register Name: MPU_TYPE Access: Read-write Reset: 0x00000800 – IREGION DREGION – SEPARATE The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. • IREGION: Instruction Region Indicates the number of supported MPU instruction regions. Always contains 0x00.
  • Page 233 SAM4S Series [Preliminary] 11.11.2.2 MPU Control Register Name: MPU_CTRL Access: Read-write Reset: 0x00000800 – – – – PRIVDEFENA HFNMIENA ENABLE The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. •...
  • Page 234 • Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1.
  • Page 235 SAM4S Series [Preliminary] 11.11.2.3 MPU Region Number Register Name: MPU_RNR Access: Read-write Reset: 0x00000800 – – – REGION The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers. • REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
  • Page 236 11.11.2.4 MPU Region Base Address Register Name: MPU_RBAR Access: Read-write Reset: 0x00000000 ADDR ADDR ADDR – VALID REGION Note: If the region size is 32B, the ADDR field is bits [31:5] and there is no Reserved field. The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR.
  • Page 237 SAM4S Series [Preliminary] 11.11.2.5 MPU Region Attribute and Size Register Name: MPU_RASR Access: Read-write Reset: 0x00000000 – – – – SIZE ENABLE The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
  • Page 238 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (SIZE+1) (Region size in bytes) = 2 The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
  • Page 239 SAM4S Series [Preliminary] 11.12 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory.
  • Page 240 Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute. Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing. Context The environment that each process operates in for a multitasking operating system.
  • Page 241 SAM4S Series [Preliminary] Halfword A 16-bit data item. Illegal instruction An instruction that is architecturally Undefined. Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual implementations. Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual implementations.
  • Page 242 Preserved Preserved by writing the same value back that has been previously read from the same field on the same processor. Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP. Region A partition of memory space.
  • Page 243 SAM4S Series [Preliminary] 12. Debug and Test Features 12.1 Description The SAM4 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs.
  • Page 244 12.3 Application Examples 12.3.1 Debug Environment Figure 12-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the pro- gram and viewing core and peripheral registers. Figure 12-2. Application Debug Environment Example Host Debugger SWJ-DP Emulator/Probe...
  • Page 245 SAM4S Series [Preliminary] Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Chip n Chip 2 Connector SAM4 Chip 1 SAM4-based Application Board In Test 12.4 Debug and Test Pin Description Table 12-1. Debug and Test Signal List Signal Name Function Type...
  • Page 246 12.5 Functional Description 12.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode.
  • Page 247 SAM4S Series [Preliminary] When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asyn- chronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 12-2. SWJ-DP Pin List Pin Name JTAG Port...
  • Page 248 • Watchpoint event to halt core The DWT contains counters for the items that follow: • Clock cycle (CYCCNT) • Folded instructions • Load Store Unit (LSU) operations • Sleep Cycles • CPI (all instruction cycles except for the first cycle) •...
  • Page 249 It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port opera- tions. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided on Atmel’s web site to set up the test.
  • Page 250 12.5.8 ID Code Register Access: Read-only VERSION PART NUMBER PART NUMBER PART NUMBER MANUFACTURER IDENTITY MANUFACTURER IDENTITY • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM4S 0x05B32 • MANUFACTURER IDENTITY[11:1] Set to 0x01F.
  • Page 251: Vddcore

    SAM4S Series [Preliminary] 13. Reset Controller (RSTC) 13.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.
  • Page 252 13.4 Functional Description 13.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer •...
  • Page 253 SAM4S Series [Preliminary] The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
  • Page 254 Figure 13-3. General Reset State SLCK Freq. backup_nreset Processor Startup = 2 cycles proc_nreset RSTTYP 0x0 = General Reset periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles 13.4.4.2 Backup Reset A Backup reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs.
  • Page 255 SAM4S Series [Preliminary] Figure 13-4. User Reset State SLCK Freq. NRST Resynch. Resynch. Processor Startup 2 cycles 2 cycles = 2 cycles proc_nreset RSTTYP 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 13.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: •...
  • Page 256 If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog- ress) is set in the Status Register (RSTC_SR).
  • Page 257 SAM4S Series [Preliminary] Figure 13-6. Watchdog Reset SLCK Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 13.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: •...
  • Page 258 13.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one.
  • Page 259 SAM4S Series [Preliminary] 13.5 Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register RSTC_CR Write-only 0x04 Status Register RSTC_SR Read-only 0x0000_0000 0x08 Mode Register RSTC_MR Read-write 0x0000 0001 11100B–ATARM–31-Jul-12...
  • Page 260 13.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1400 Access: Write-only – – – – – – – – – – – – – – – – – – – – EXTRST PERRST – PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor.
  • Page 261 SAM4S Series [Preliminary] 13.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1404 Access: Read-only – – – – – – – – – – – – – – SRCMP NRSTL – – – – – RSTTYP – – – – –...
  • Page 262 13.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1408 Access: Read-write – – – – – – – – – – – – ERSTL – – URSTIEN – – – URSTEN • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
  • Page 263 SAM4S Series [Preliminary] 14. Real-time Timer (RTT) 14.1 Description The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 Embedded Characteristics •...
  • Page 264 14.4 Functional Description The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz).
  • Page 265 SAM4S Series [Preliminary] Figure 14-2. RTT Counting APB cycle APB cycle SCLK RTPRES - 1 Prescaler ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 11100B–ATARM–31-Jul-12...
  • Page 266 14.5 Real-Time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read-write 0x0000_8000 0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 267 SAM4S Series [Preliminary] 14.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1430 Access: Read-write – – – – – – – – – – – – – RTTRST RTTINCIEN ALMIEN RTPRES RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 2 * SCLK period.
  • Page 268 14.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1434 Access: Read-write ALMV ALMV ALMV ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 269 SAM4S Series [Preliminary] 14.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0x400E1438 Access: Read-only CRTV CRTV CRTV CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 11100B–ATARM–31-Jul-12...
  • Page 270 14.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E143C Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 271 SAM4S Series [Preliminary] 15. Real Time Clock (RTC) 15.1 Description The Real-Time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Per- sian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
  • Page 272 15.3 Block Diagram Figure 15-1. RTC Block Diagram 32768 Divider Slow Clock: SLCK RTCOUT0 Wave Time Date Generator RTCOUT1 Clock Calibration Entry Interrupt User Interface Alarm RTC Interrup Control Control SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 273 SAM4S Series [Preliminary] 15.4 Product Dependencies 15.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 15.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first.
  • Page 274 15.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register.
  • Page 275 SAM4S Series [Preliminary] Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power consider- ations).
  • Page 276 Figure 15-2. Update Sequence Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD = 1 ? Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR SAM4S Series [Preliminary]...
  • Page 277 SAM4S Series [Preliminary] 15.5.7 RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration cir- cuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20-25°C).
  • Page 278 15.5.8 Waveform Generation Waveforms can be generated by the RTC in order to take advantage of the RTC inherent pres- calers while the RTC is the only powered circuitry (low power mode of operation, backup mode) or in any active modes. Going into backup or low power operating modes does not affect the waveform generation outputs.
  • Page 279 SAM4S Series [Preliminary] Figure 15-3. Waveform Generation ‘0’ ‘0’ 1 Hz 1 Hz 32 Hz 32 Hz 64 Hz 64 Hz RTCOUT0 RTCOUT1 512 Hz 512 Hz toggle_alarm toggle_alarm flag_alarm flag_alarm pulse pulse RTC_MR(OUT0) RTC_MR(OUT1) alarm match alarm match event 2 event 1 flag_alarm RTC_SCCR(ALRCLR)
  • Page 280 15.6 Real-Time Clock (RTC) User Interface Table 15-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register RTC_CR Read-write 0x04 Mode Register RTC_MR Read-write 0x08 Time Register RTC_TIMR Read-write 0x0C Calendar Register RTC_CALR Read-write 0x01A11020 0x10 Time Alarm Register RTC_TIMALR Read-write 0x14...
  • Page 281 SAM4S Series [Preliminary] 15.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1460 Access: Read-write – – – – – – – – – – – – – – CALEVSEL – – – – – – TIMEVSEL – – – – – –...
  • Page 282 15.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1464 Access: Read-write – – TPERIOD – THIGH – OUT1 – OUT0 HIGHPPM CORRECTION – – – NEGPPM – – PERSIAN HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. •...
  • Page 283 SAM4S Series [Preliminary] The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
  • Page 284 • THIGH: High Duration of the Output Pulse Value Name Description H_31MS 31.2 ms H_16MS 15.6 ms H_4MS 3.91 ms H_976US 976 µs H_488US 488 µs H_122US 122 µs H_30US 30.5 µs H_15US 15.2 µs • TPERIOD: Period of the Output Pulse Value Name Description...
  • Page 285 SAM4S Series [Preliminary] 15.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1468 Access: Read-write – – – – – – – – – AMPM HOUR – – • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
  • Page 286 15.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E146C Access: Read-write – – DATE MONTH YEAR – CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. •...
  • Page 287 SAM4S Series [Preliminary] 15.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1470 Access: Read-write – – – – – – – – HOUREN AMPM HOUR MINEN SECEN • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. •...
  • Page 288 15.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1474 Access: Read-write DATEEN – DATE MTHEN – – MONTH – – – – – – – – – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. •...
  • Page 289 SAM4S Series [Preliminary] 15.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1478 Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – – TDERR CALEV TIMEV ALARM...
  • Page 290 15.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E147C Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR...
  • Page 291 SAM4S Series [Preliminary] 15.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1480 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – TDERREN CALEN TIMEN...
  • Page 292 15.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1484 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS...
  • Page 293 SAM4S Series [Preliminary] 15.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1488 Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 294 15.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E148C Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – – – – NVCALALR NVTIMALR NVCAL NVTIM...
  • Page 295 SAM4S Series [Preliminary] 16. Watchdog Timer (WDT) 16.1 Description The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz).
  • Page 296 16.3 Block Diagram Figure 16-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 12-bit Down Counter WDT_MR reload Current SLCK 1/128 Value <= WDD WDT_MR WDRSTEN wdt_fault (to Reset Controller) WDUNF wdt_int reset WDERR read WDT_SR WDFIEN reset WDT_MR reset SAM4S Series [Preliminary]...
  • Page 297 SAM4S Series [Preliminary] 16.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR).
  • Page 298 Figure 16-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 Normal behavior if WDRSTEN is 0 Forbidden Window Permitted Window WDT_CR = WDRSTT Watchdog Fault SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 299 SAM4S Series [Preliminary] 16.5 Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000 11100B–ATARM–31-Jul-12...
  • Page 300 16.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0x400E1450 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog.
  • Page 301 SAM4S Series [Preliminary] 16.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0x400E1454 Access: Read-write Once WDIDLEHLT WDDBGHLT WDDIS WDRPROC WDRSTEN WDFIEN • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
  • Page 302 16.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0x400E1458 Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 303 SAM4S Series [Preliminary] 17. Supply Controller (SUPC) 17.1 Description The Supply Controller (SUPC) controls the supply voltage of the Core of the system and man- ages the Backup Low Power Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention.
  • Page 304 17.3 Block Diagram Figure 17-1. Supply Controller Block Diagram VDDIO VDDOUT vr_on Software Controlled vr_mode VDDIN Voltage Regulator VDDIO Supply Zero-Power Controller Power-on Reset PIOA/B/C PIOx Input/Output Buffers Supply Monitor (Backup) Analog WKUP0 - WKUP15 Comparator General Purpose ADC Analog Backup Registers Circuitry ADVREF...
  • Page 305 SAM4S Series [Preliminary] 17.4 Supply Controller Functional Description 17.4.1 Supply Controller Overview The device can be divided into two power supply areas: • The VDDIO Power Supply: including the Supply Controller, a part of the Reset Controller, the Slow Clock switch, the General Purpose Backup Registers, the Supply Monitor and the Clock which includes the Real Time Timer and the Real Time Clock •...
  • Page 306 17.4.2 Slow Clock Generator The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
  • Page 307 SAM4S Series [Preliminary] When the user does not use the internal voltage regulator and wants to supply VDDCORE by an external supply, it is possible to disable the voltage regulator. Note that it is different from the Backup mode. Depending on the application, disabling the voltage regulator can reduce power consumption as the voltage regulator input (VDDIN) is shared with the ADC and DAC.
  • Page 308 Figure 17-2. Supply Monitor Status Bit and Associated Interrupt Continuous Sampling (SMSMPL = 1) Periodic Sampling Supply Monitor ON 3.3 V Threshold Read SUPC_SR SMS and SUPC interrupt 17.4.5 Power Supply Reset 17.4.5.1 Raising the Power Supply As soon as the voltage VDDIO rises, the RC oscillator is powered up and the zero-power power- on reset cell maintains its output low as long as VDDIO has not reached its target voltage.
  • Page 309 SAM4S Series [Preliminary] Figure 17-3. Raising the VDDIO Power Supply Voltage 3 x Slow Clock 3 x Slow Clock 6.5 x Slow Clock 7 x Slow Clock Cycles Regulator Cycles Cycles Cycles Zero-Power POR Backup Power Supply Zero-Power Power-On Reset Cell output 22 - 42 kHz RC Oscillator output vr_on...
  • Page 310 17.4.6.2 Brownout Detector Reset The brownout detector provides the bodcore_in signal to the SUPC which indicates that the volt- age regulation is operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled, the Supply Controller can assert vddcore_nreset. This feature is enabled by writing the bit, BODRSTEN (Brownout Detector Reset Enable) to 1 in the Supply Controller Mode Register (SUPC_MR).
  • Page 311 SAM4S Series [Preliminary] 17.4.7.1 Wake Up Inputs The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core power supply. Each input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to WKUPEN 15, in the Wake Up Inputs Register (SUPC_WUIR).
  • Page 312 Figure 17-5. Low Power Debouncer (Push-to-Make switch, pull-up resistors) AT91SAM RTCOUT0 Pull-Up Resistor WKU P0 Pull-Up Resistor WKU P1 Figure 17-6. Low Power Debouncer (Push-to-Break switch, pull-down resistors) AT91SAM RTCOUT0 WKU P0 WKU P1 Pull-Down Resistors The debouncing parameters can be adjusted and are shared (except the wake up input polarity) by both debouncers.
  • Page 313 SAM4S Series [Preliminary] In order to determine which wake up pin triggers the core wake up or simply which debouncer triggers an event, a status flag is associated for each low power debouncer. These 2 flags can be read in the SUPC_SR. A debounce event can perform an immediate clear (0 delay) on first half the general purpose backup registers (GPBR).
  • Page 314 17.5 Supply Controller (SUPC) User Interface The User Interface of the Supply Controller is a part of the System Controller User Interface. 17.5.1 System Controller (SYSC) User Interface Table 17-1. System Controller Registers Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller...
  • Page 315 SAM4S Series [Preliminary] 17.5.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1410 Access: Write-only – – – – – – – – – – – – – – – – – – – XTALSEL VROFF – – • VROFF: Voltage Regulator Off 0 (NO_EFFECT) = no effect.
  • Page 316 17.5.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1414 Access: Read-write – – – – – – – – – – – – – – – – – – SMIEN SMRSTEN – SMSMPL – – – – SMTH •...
  • Page 317 SAM4S Series [Preliminary] 17.5.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1418 Access: Read-write – – – OSCBYPASS – – – – – ONREG BODDIS BODRSTEN – – – – – – – – – – – – • BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset”...
  • Page 318 17.5.6 Supply Controller Wake Up Mode Register Name: SUPC_WUMR Address: 0x400E141C Access: Read-write – – – – – – – – – – – – – LPDBC – WKUPDBC – – – – LPDBCCLR LPDBCEN1 LPDBCEN0 – RTCEN RTTEN SMEN –...
  • Page 319 SAM4S Series [Preliminary] Value Name Description IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 4096_SCLK...
  • Page 320 17.5.7 System Controller Wake Up Inputs Register Name: SUPC_WUIR Address: 0x400E1420 Access: Read-write WKUPT15 WKUPT14 WKUPT13 WKUPT12 WKUPT11 WKUPT10 WKUPT9 WKUPT8 WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT3 WKUPT2 WKUPT1 WKUPT0 WKUPEN15 WKUPEN14 WKUPEN13 WKUPEN12 WKUPEN11 WKUPEN10 WKUPEN9 WKUPEN8 WKUPEN7 WKUPEN6 WKUPEN5 WKUPEN4 WKUPEN3 WKUPEN2...
  • Page 321: Vddio

    SAM4S Series [Preliminary] 17.5.8 Supply Controller Status Register Name: SUPC_SR Address: 0x400E1424 Access: Read-write WKUPIS15 WKUPIS14 WKUPIS13 WKUPIS12 WKUPIS11 WKUPIS10 WKUPIS9 WKUPIS8 WKUPIS7 WKUPIS6 WKUPIS5 WKUPIS4 WKUPIS3 WKUPIS2 WKUPIS1 WKUPIS0 – LPDBCS1 LPDBCS0 – – – – – OSCSEL SMOS SMRSTS BODRSTS SMWS...
  • Page 322 • OSCSEL: 32-kHz Oscillator Selection Status 0 (RC) = the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 1 (CRYST) = the slow clock, SLCK is generated by the 32-kHz crystal oscillator. • LPDBCS0: Low Power Debouncer Wake Up Status on WKUP0 0 (NO) = no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
  • Page 323 SAM4S Series [Preliminary] 18. General Purpose Backup Registers (GPBR) 18.1 Description The System Controller embeds Eight general-purpose backup registers. 18.2 Embedded Characteristics • Eight 32-bit General Purpose Backup Registers 18.3 General Purpose Backup Registers (GPBR) User Interface Table 18-1. Register Mapping Offset Register Name...
  • Page 324 18.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1490 Access: Read-write GPBR_VALUE GPBR_VALUE GPBR_VALUE GPBR_VALUE • GPBR_VALUE: Value of GPBR x SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 325 SAM4S Series [Preliminary] 19. Enhanced Embedded Flash Controller (EEFC) 19.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the pro- gramming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
  • Page 326 19.3 Product Dependencies 19.3.1 Power Management The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Man- agement Controller has no effect on its behavior. 19.3.2 Interrupt Sources The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Nested Vectored Interrupt Controller (NVIC).
  • Page 327 SAM4S Series [Preliminary] 19.4 Functional Description 19.4.1 Embedded Flash Organization The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of: • One memory plane organized in several pages of the same size. • Two 128-bit or 64-bit read buffers used for code read optimization. •...
  • Page 328 19.4.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb2 mode by means of the 128- or 64- bit wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.
  • Page 329 SAM4S Series [Preliminary] Figure 19-2. Code Read Optimization for FWS = 0 Master Clock ARM Request (32-bit) @Byte 0 @Byte 4 @Byte 8 @Byte 12 @Byte 16 @Byte 20 @Byte 24 @Byte 28 @Byte 32 Flash Access Bytes 0-15 Bytes 16-31 Bytes 32-47 Buffer 0 (128bits) Bytes 0-15...
  • Page 330 Afterwards, combining the sequential prefetch (described in Section 19.4.2.2 ”Code Read Opti- mization”) through the loop body with the fast read access to the loop entry cache, the whole loop can be iterated with no wait-state. Figure 19-4. Code Loops Optimization Backward address jump Flash Memory 128-bit words...
  • Page 331 SAM4S Series [Preliminary] 19.4.3 Flash Commands The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as program- ming the memory Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash erasing, etc. Table 19-2. Set of Commands Command Value...
  • Page 332 When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read access to the EEFC_FSR register. Figure 19-6.
  • Page 333 SAM4S Series [Preliminary] 19.4.3.1 Getting Embedded Flash Descriptor This command allows the system to learn about the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration.
  • Page 334 Data are written to the latch buffer before the programming command is written to the Flash Command Register EEFC_FCR. The sequence is as follows: • Write the full page, at any page address, within the internal memory area address space. •...
  • Page 335 SAM4S Series [Preliminary] • Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. FARG must be set with a page number that is in the sector to be erased. The processor must not fetch code from the Flash memory. The erase sequence is: •...
  • Page 336 It is possible to clear lock bits previously set. Then the locked region can be erased or pro- grammed. The unlock sequence is: • The Clear Lock command (CLB) and a page number to be unprotected are written in the Flash Command Register.
  • Page 337 SAM4S Series [Preliminary] • Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is: • Start the Clear GPNVM Bit command (CGPB) by writing the Flash Command Register with CGPB and the number of the GPNVM bit to be cleared.
  • Page 338 The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit command. The table below shows the bit implementation for each frequency: RC Calibration Frequency EEFC_FRR Bits 8 MHz output [28 - 22] 12 MHz output [38 - 32] The RC calibration for 4 MHz is set to 1,000,000.
  • Page 339 SAM4S Series [Preliminary] • The User Signature is located in the first 512 bytes of the Flash memory mapping, thus, at the address 0x00400000-0x004001FF. • To stop the User Signature mode, the user needs to send the Stop Read User Signature command (SPUS) by writing the Flash Command Register with the SPUS command.
  • Page 340 19.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with the base address of 0x400E0A00 Table 19-5. Register Mapping Offset Register Name Access Reset State EEFC EEFC 0x00...
  • Page 341 SAM4S Series [Preliminary] 19.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 Access: Read-write Offset: 0x00 – – – – – CLOE – – – – – – – – SCOD – – – – – – – – – –...
  • Page 342 19.5.2 EEFC Flash Command Register Name: EEFC_FCR Address: 0x400E0A04 Access: Write-only Offset: 0x04 FKEY FARG FARG FCMD • FCMD: Flash Command This field defines the Flash commands. Refer to “Flash Commands” on page 331. • FARG: Flash Command Argument Field is meaningless. Erase all command FARG must be set with a page number that is in the Erase plane command...
  • Page 343 SAM4S Series [Preliminary] 19.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 Access: Read-only Offset: 0x08 – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 344 19.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C Access: Read-only Offset: 0x0C FVALUE FVALUE FVALUE FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read.
  • Page 345 SAM4S Series [Preliminary] 20. Fast Flash Programming Interface (FFPI) 20.1 Description The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is con- sidered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
  • Page 346: Vddcore

    20.2 Parallel Fast Flash Programming 20.2.1 Device Configuration In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode.
  • Page 347 SAM4S Series [Preliminary] Table 20-1. Signal Description List (Continued) Active Signal Name Function Type Level Comments PGMNOE Output Enable (active high) Input Pulled-up input at reset 0: DATA[15:0] is in input mode PGMNVALID Output Pulled-up input at reset 1: DATA[15:0] is in output mode PGMM[3:0] Specifies DATA type (See Table...
  • Page 348 Table 20-3. Command Bit Coding (Continued) DATA[15:0] Symbol Command Executed 0x0035 Get Security Bit 0x001F WRAM Write Memory 0x001E Get Version 20.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE and VDDPLL. •...
  • Page 349 SAM4S Series [Preliminary] Table 20-4. Write Handshake Step Programmer Action Device Action Data I/O Sets MODE and DATA signals Waits for NCMD low Input Clears NCMD signal Latches MODE and DATA Input Waits for RDY low Clears RDY signal Input Releases MODE and DATA signals Executes command and polls NCMD high Input...
  • Page 350 Table 20-5. Read Handshake (Continued) Step Programmer Action Device Action DATA I/O Sets NOE signal Output Waits for NVALID high Sets DATA bus in input mode Sets DATA in output mode Sets NVALID signal Input Sets NCMD signal Waits for NCMD high Input Waits for RDY high Sets RDY signal...
  • Page 351 SAM4S Series [Preliminary] • Before access to any page other than the current one • When a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 20-7.
  • Page 352 In the same way, the Clear Lock command (CLB) is used to clear lock bits. Table 20-9. Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] Write handshaking CMDE SLB or CLB Write handshaking DATA Bit Mask Lock bits can be read using the Get Lock Bit command (GLB). The n lock bit is active when the bit n of the bit mask is set..
  • Page 353 SAM4S Series [Preliminary] Table 20-13. Set Security Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] Write handshaking CMDE Write handshaking DATA Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash.
  • Page 354 20.2.5.8 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-15. Get Version Command Step Handshake Sequence MODE[3:0] DATA[15:0] Write handshaking CMDE Write handshaking DATA Version SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 355 SAM4S Series [Preliminary] 21. Cortex M Cache Controller (CMCC) (ONLY FOR SAM4SD32/SD16/SA16) 21.1 Description The Cortex M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, tag directory, data memory, metadata memory and a configuration interface.
  • Page 356 21.3 Block Diagram Figure 21-1. Block Diagram Cortex M Memory Interface Bus Cortex M Interface Cache METADATA RAM Controller DATA RAM Interface Cortex M Registers Interface TAG RAM Memory Interface System Memory Bus SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 357 SAM4S Series [Preliminary] 21.4 Functional Description 21.4.1 Cache Operation On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated through the use of its configuration registers. The configuration interface is memory mapped in the private peripheral bus.
  • Page 358 21.5 Cortex M Cache Controller (CMCC) User Interface Table 21-1. Register Mapping Offset Register Name Access Reset 0x00 Cache Type Register CMCC_TYPE Read-only – 0x04 Cache Configuration Register CMCC_CFG Read-write 0x00000000 0x08 Cache Control Register CMCC_CTRL Write-only 0x00000000 0x0C Cache Status Register CMCC_SR Read-only 0x00000000...
  • Page 359 SAM4S Series [Preliminary] 21.5.1 Cache Controller Type Register Name: CMCC_TYPE Address: 0x4007C000 Access: Read-only – – – – – – – – – – – – – – – – – CLSIZE CSIZE LCKDOWN WAYNUM LRUP RANDP GCLK • AP: Access Port Access Allowed 0: Access Port Access is disabled.
  • Page 360 • LCKDOWN: Lock Down Supported 0: Lock Down is not supported. 1: Lock Down is supported. • CSIZE: Cache Size Value Name Description CSIZE_1KB Cache Size 1 KBytes CSIZE_2KB Cache Size 2 KBytes CSIZE_4KB Cache Size 4 KBytes CSIZE_8KB Cache Size 8 KBytes •...
  • Page 361 SAM4S Series [Preliminary] 21.5.2 Cache Controller Configuration Register Name: CMCC_CFG Address: 0x4007C004 Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 362 21.5.4 Cache Controller Status Register Name: CMCC_SR Address: 0x4007C00C Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 363 SAM4S Series [Preliminary] 21.5.5 Cache Controller Maintenance Register 0 Name: CMCC_MAINT0 Address: 0x4007C020 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 364 21.5.6 Cache Controller Maintenance Register 1 Name: CMCC_MAINT1 Address: 0x4007C024 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – INDEX – – – – • INDEX: Invalidate Index This field indicates the cache line that is being invalidated.
  • Page 365 SAM4S Series [Preliminary] 21.5.7 Cache Controller Monitor Configuration Register Name: CMCC_MCFG Address: 0x4007C028 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 366 21.5.8 Cache Controller Monitor Enable Register Name: CMCC_MEN Address: 0x4007C02C Access: Write-only Reset: 0x00002000 – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 367 SAM4S Series [Preliminary] 21.5.9 Cache Controller Monitor Control Register Name: CMCC_MCTRL Address: 0x4007C030 Access: Write-only Reset: 0x00002000 – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 368 21.5.10 Cache Controller Monitor Status Register Name: CMCC_MSR Address: 0x4007C034 Access: Write-only Reset: 0x00002000 EVENT_CNT EVENT_CNT EVENT_CNT EVENT_CNT • EVENT_CNT: Monitor Event Counter SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 369 SAM4S Series [Preliminary] 22. Cyclic Redundancy Check Calculation Unit (CRCCU) 22.1 Description The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the Bus Matrix. 22.2 Embedded Characteristics • 32-bit cyclic redundancy check automatic calculation •...
  • Page 370 22.3 CRCCU Block Diagram Figure 22-1. Block Diagram Host Atmel Interface APB Bus Context FSM CRC Register Addr Register Data Register HRDATA AHB Interface HTRANS HSIZE AHB-Layer External Flash AHB SRAM Bus Interface SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 371 SAM4S Series [Preliminary] 22.4 Product Dependencies 22.4.1 Power Management The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the CRCCU in the PMC to enable the CRCCU clock. 22.4.2 Interrupt Source The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires programming the Interrupt Controller before configuring the CRCCU.
  • Page 372 The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decre- mented if its value is different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In this case, the relevant CRCCU DMA Status Register bit, DMASR, is automatically cleared.
  • Page 373 SAM4S Series [Preliminary] 22.6 Transfer Control Registers Memory Mapping Table 22-2. Transfer Control Register Memory Mapping Offset Register Name Access CRCCU_DSCR + 0x0 CRCCU Transfer Address Register TR_ADDR Read-write CRCCU_DSCR + 0x4 CRCCU Transfer Control Register TR_CTRL Read-write CRCCU_DSCR + 0xC - 0x10 Reserved CRCCU_DSCR+0x10 CRCCU Transfer Reference Register...
  • Page 374 22.6.1 Transfer Address Register Name: TR_ADDR Access: Read-write Reset: 0x00000000 ADDR ADDR ADDR ADDR • ADDR: Transfer Address SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 375 SAM4S Series [Preliminary] 22.6.2 Transfer Control Register Name: TR_CTRL Access: Read-write Reset: 0x00000000 – – – – – TRWIDTH – – – – – – – – BTSIZE BTSIZE • BTSIZE: Buffer Transfer Size • TRWIDTH: Transfer Width Register TRWIDTH Single Transfer Size BYTE HALFWORD...
  • Page 376 22.6.3 Transfer Reference Register Name: TR_CRC Access: Read-write Reset: 0x00000000 REFCRC REFCRC REFCRC REFCRC • REFCRC: Reference CRC When Compare mode is enabled, the checksum is compared with that register. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 377 SAM4S Series [Preliminary] 22.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface Table 22-3. Register Mapping Offset Register Name Access Reset 0x00000000 CRCCU Descriptor Base Register CRCCU_DSCR Read-write 0x00000000 0x00000004 Reserved 0x00000008 CRCCU DMA Enable Register CRCCU_DMA_EN Write-only 0x00000000 0x0000000C CRCCU DMA Disable Register CRCCU_DMA_DIS Write-only...
  • Page 378 22.7.1 CRCCU Descriptor Base Address Register Name: CRCCU_DSCR Address:0x40044000 Access: Read-write Reset: 0x00000000 DSCR DSCR DSCR – – – – – – – – – • DSCR: Descriptor Base Address DSCR needs to be aligned with 512-byte boundaries. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 379 SAM4S Series [Preliminary] 22.7.2 CRCCU DMA Enable Register Name: CRCCU_DMA_EN Address:0x40044008 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 380 22.7.3 CRCCU DMA Disable Register Name: CRCCU_DMA_DIS Address:0x4004400C Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 381 SAM4S Series [Preliminary] 22.7.4 CRCCU DMA Status Register Name: CRCCU_DMA_SR Address:0x40044010 Access: Read-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 382 22.7.5 CRCCU DMA Interrupt Enable Register Name: CRCCU_DMA_IER Address:0x40044014 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 383 SAM4S Series [Preliminary] 22.7.6 CRCCU DMA Interrupt Disable Register Name: CRCCU_DMA_IDR Address:0x40044018 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 384 22.7.7 CRCCU DMA Interrupt Mask Register Name: CRCCU_DMA_IMR Address:0x4004401C Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 385 SAM4S Series [Preliminary] 22.7.8 CRCCU DMA Interrupt Status Register Name: CRCCU_DMA_ISR Address:0x40044020 Access: Read-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 386 22.7.9 CRCCU Control Register Name: CRCCU_CR Address:0x40044034 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 387 SAM4S Series [Preliminary] 22.7.10 CRCCU Mode Register Name: CRCCU_MR Address:0x40044038 Access: Read Write Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – DIVIDER PTYPE COMPARE ENABLE...
  • Page 388 22.7.11 CRCCU Status Register Name: CRCCU_SR Address:0x4004403C Access: Read-only Reset: 0x00000000 • CRC: Cyclic Redundancy Check Value This register can not be read if the COMPARE field of the CRC_MR register is set to true. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 389 SAM4S Series [Preliminary] 22.7.12 CRCCU Interrupt Enable Register Name: CRCCU_IER Address:0x40044040 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 390 22.7.13 CRCCU Interrupt Disable Register Name: CRCCU_IDR Address:0x40044044 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 391 SAM4S Series [Preliminary] 22.7.14 CRCCU Interrupt Mask Register Name: CRCCU_IMR Address:0x40044048 Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 392 22.7.15 CRCCU Interrupt Status Register Name: CRCCU_ISR Address:0x4004404C Access: Read-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 393 SAM4S Series [Preliminary] 23. SAM4S Boot Program 23.1 Description The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 23.2 Hardware and Software Constraints • SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code.
  • Page 394 If a clock is found from the two possible sources above, the boot program checks to verify that the frequency is one of the supported external frequencies. If the frequency is one of the sup- ported external frequencies, USB activation is allowed, else (no clock or frequency other than one of the supported external frequencies), the internal 12 MHz RC oscillator is used as main clock and USB clock is not allowed due to frequency drift of the 12 MHz RC oscillator.
  • Page 395 SAM4S Series [Preliminary] 23.5 SAM-BA Monitor The SAM-BA boot principle: Once the communication interface is identified, to run in an infinite loop waiting for different com- mands as shown in Table 23-2. Table 23-2. Commands Available through the SAM-BA Boot Command Action Argument(s)
  • Page 396 • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 23.5.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate.
  • Page 397 "Unauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID Numbers is strictly prohibited." Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details.
  • Page 398 23.5.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM- BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver.
  • Page 399 SAM4S Series [Preliminary] 24. Bus Matrix (MATRIX) 24.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 4 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is con- nected directly (zero cycle latency).
  • Page 400 24.2.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table Table 24-3.
  • Page 401 SAM4S Series [Preliminary] To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that allow to set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR.
  • Page 402 A predicted end of burst is used for defined length burst transfer, which is selected between the following: 1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.
  • Page 403 SAM4S Series [Preliminary] 24.5.2.3 Round-Robin arbitration with fixed default master This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master.
  • Page 404 24.8 Bus Matrix (MATRIX) User Interface Table 24-4. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000000 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read-write...
  • Page 405 SAM4S Series [Preliminary] 24.8.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0..MATRIX_MCFG3 Address: 0x400E0200 Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 406 24.8.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0..MATRIX_SCFG4 Address: 0x400E0240 Access: Read-write – – – – – – ARBT – – – FIXED_DEFMSTR DEFMSTR_TYPE – – – – – – – – SLOT_CYCLE • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reach for a burst it may be broken by another master trying to access this slave.
  • Page 407 SAM4S Series [Preliminary] 24.8.3 Bus Matrix Priority Registers For Slaves Name: MATRIX_PRAS0..MATRIX_PRAS4 Address: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3], 0x400E02A0 [4] Access: Read-write – – – – – – – – – – – – – – M4PR –...
  • Page 408 24.8.4 System I/O Configuration Register Name: CCFG_SYSIO Address: 0x400E0314 Access Read-write Reset: 0x0000_0000 – – – – – – – – – – – – – – – – – – – SYSIO12 SYSIO11 SYSIO10 – – SYSIO7 SYSIO6 SYSIO5 SYSIO4 –...
  • Page 409 SAM4S Series [Preliminary] 24.8.5 SMC NAND Flash Chip select Configuration Register Name: CCFG_SMCNFCS Address: 0x400E031C Type: Read-write Reset: 0x0000_0000 – – – – – – – – – – – – – – – – – – – – – –...
  • Page 410 24.8.6 Write Protect Mode Register Name: MATRIX_WPMR Address: 0x400E03E4 Access: Read-write WPKEY WPKEY WPKEY – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 24.7 “Write Protect Registers” on page 403. • WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT”...
  • Page 411 SAM4S Series [Preliminary] 24.8.7 Write Protect Status Register Name: MATRIX_WPSR Address: 0x400E03E8 Access: Read-only – – – – – – – – WPVSRC WPVSRC – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 24.7 “Write Protect Registers” on page 403.
  • Page 412 SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 413 SAM4S Series [Preliminary] 25. Static Memory Controller (SMC) 25.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the Cortex-M4 based device. The External Bus Interface of the SAM4S consists of a Static Memory Controller (SMC). This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
  • Page 414 25.3 I/O Lines Description Table 25-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Read Signal Output Write Enable Signal Output A[23:0] Address Bus Output D[7:0] Data Bus NWAIT External Wait Signal Input NANDCS NAND Flash Chip Select Line...
  • Page 415 SAM4S Series [Preliminary] 25.4 Product Dependencies 25.4.1 I/O Lines The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.
  • Page 416 25.6 Connection to External Devices 25.6.1 Data Bus Width The data bus width is 8 bits. Figure 25-2 shows how to connect a 512K x 8-bit memory on NCS2. Figure 25-2. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:0] A[18:0] Write Enable...
  • Page 417 SAM4S Series [Preliminary] Note that when NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO Mode but only in peripheral mode (NWE function). If NWE function is not used for other external memories (SRAM, LCD), it must be configured in one of the following modes. •...
  • Page 418 Figure 25-4. Standard and “CE don’t care” NAND Flash Application Examples D[7:0] D[7:0] AD[7:0] AD[7:0] A[22:21] A[22:21] NCSx NCSx Not Connected NAND Flash “CE don’t care” NAND Flash NANDOE NANDOE NANDWE NANDWE SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 419 SAM4S Series [Preliminary] 25.7 Application Example 25.7.1 Implementation Examples Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for memory device availability. For hardware implementation examples, refer to SAM4S-EK schematics, which show examples of a connection to an LCD module and NAND Flash.
  • Page 420 25.7.1.2 NOR Flash Hardware Configuration D[0..7] A[0..21] VCCQ NRST RESET 100NF 100NF NCS0 100NF 100NF Software Configuration Configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 421 SAM4S Series [Preliminary] 25.8 Standard Read and Write Protocols In the following sections, NCS represents one of the NCS[0..3] chip select lines. 25.8.1 Read Waveforms The read cycle is shown on Figure 25-5. The read cycle starts with the address setting on the memory address bus. Figure 25-5.
  • Page 422 25.8.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of...
  • Page 423 SAM4S Series [Preliminary] 25.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 25.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus.
  • Page 424 Figure 25-8. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS A[23:0] PACC D[7:0] Data Sampling 25.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 25-9. The write cycle starts with the address setting on the memory address bus.
  • Page 425 SAM4S Series [Preliminary] Figure 25-9. Write Cycle A [23:0] NWE_SETUP NWE_PULSE NWE_HOLD NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE 25.8.3.3 Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD...
  • Page 426 Figure 25-10. Null Setup and Hold Values of NCS and NWE in Write Cycle A [23:0] D[7:0] NWE_PULSE NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE NWE_CYCLE 25.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
  • Page 427 SAM4S Series [Preliminary] Figure 25-11. WRITE_MODE = 1. The write operation is controlled by NWE A [23:0] D[7:0] 25.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 25-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal.
  • Page 428 The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR). List of the write-protected registers: • Section 25.15.1 ”SMC Setup Register” • Section 25.15.2 ”SMC Pulse Register” • Section 25.15.3 ”SMC Cycle Register” • Section 25.15.4 ”SMC MODE Register” 25.8.6 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one...
  • Page 429 SAM4S Series [Preliminary] 25.8.8 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre- dictable behavior of the SMC. For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and...
  • Page 430 During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1. Figure 25-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. Figure 25-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 A[23:0] NCS0 NCS2...
  • Page 431 SAM4S Series [Preliminary] Figure 25-14. Early Read Wait State: Write with No Hold Followed by Read with No Setup A[23:0] no hold no setup D[7:0] write cycle read cycle Early Read wait state Figure 25-15. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup A[23:0] no hold no setup...
  • Page 432 Figure 25-16. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle A[25:2] internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 D[7:0] write cycle Early Read read cycle (WRITE_MODE = 1) wait state...
  • Page 433 SAM4S Series [Preliminary] 25.10.3.2 Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 444). 25.10.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
  • Page 434 Figure 25-17. TDF Period in NRD Controlled Read Access (TDF = 2) A[23:0] tpacc D[7:0] TDF = 2 clock cycles NRD controlled read operation Figure 25-18. TDF Period in NCS Controlled Read Operation (TDF = 3) A[23:0] tpacc D[7:0] TDF = 3 clock cycles NCS controlled read operation 25.11.2 TDF Optimization Enabled (TDF_MODE = 1)
  • Page 435 SAM4S Series [Preliminary] Figure 25-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6;...
  • Page 436 Figure 25-20. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects A[ 23:0] read1 controlling signal (NRD) read1 hold = 1 read2 setup = 1 read2 controlling signal (NRD) TDF_CYCLES = 6 D[7:0] 5 TDF WAIT STATES read 2 cycle...
  • Page 437 SAM4S Series [Preliminary] Figure 25-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select A[23:0] read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal TDF_CYCLES = 5 (NWE) D[7:0] 4 TDF WAIT STATES...
  • Page 438 25.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select.
  • Page 439 SAM4S Series [Preliminary] Figure 25-23. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) A [23:0] FROZEN STATE D[7:0] NWAIT internally synchronized NWAIT signal Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 11100B–ATARM–31-Jul-12...
  • Page 440 Figure 25-24. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) A [23:0] FROZEN STATE NWAIT internally synchronized NWAIT signal Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 441 SAM4S Series [Preliminary] 25.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 25-25 Figure...
  • Page 442 Figure 25-26. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) A[23:0] Wait STATE NWAIT internally synchronized NWAIT signal Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 443 SAM4S Series [Preliminary] 25.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle.
  • Page 444 25.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied.
  • Page 445 SAM4S Series [Preliminary] Figure 25-29. Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC A [23:0] NWE_CYCLE = 3 NWE_CYCLE = 7 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE NORMAL MODE WRITE This write cycle finishes with the slow clock mode set Slow clock mode...
  • Page 446 25.14 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory.
  • Page 447 SAM4S Series [Preliminary] The NRD and NCS signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register.
  • Page 448 Figure 25-32. Access to Non-Sequential Data within the Same Page Page address A[23:3] A[2], A1, A0 D[7:0] NRD_PULSE NCS_RD_PULSE NRD_PULSE SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 449 SAM4S Series [Preliminary] 25.15 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 25-6. For each chip select, a set of 4 registers is used to pro- gram the parameters of the external device connected on it. In Table 25-6, “CS_number”...
  • Page 450 25.15.1 SMC Setup Register Name: SMC_SETUP[0..3] Address: 0x400E0000 [0], 0x400E0010 [1], 0x400E0020 [2], 0x400E0030 [3], 0x400E0040 [4] Access: Read-write – – NCS_RD_SETUP – – NRD_SETUP – – NCS_WR_SETUP – – NWE_SETUP • NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles •...
  • Page 451 SAM4S Series [Preliminary] 25.15.2 SMC Pulse Register Name: SMC_PULSE[0..3] Address: 0x400E0004 [0], 0x400E0014 [1], 0x400E0024 [2], 0x400E0034 [3], 0x400E0044 [4] Access: Read-write – NCS_RD_PULSE – NRD_PULSE – NCS_WR_PULSE – NWE_PULSE • NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle.
  • Page 452 25.15.3 SMC Cycle Register Name: SMC_CYCLE[0..3] Address: 0x400E0008 [0], 0x400E0018 [1], 0x400E0028 [2], 0x400E0038 [3], 0x400E0048 [4] Access: Read-write – – – – – – – NRD_CYCLE NRD_CYCLE – – – – – – – NWE_CYCLE NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
  • Page 453 SAM4S Series [Preliminary] 25.15.4 SMC MODE Register Name: SMC_MODE[0..3] Address: 0x400E000C [0], 0x400E001C [1], 0x400E002C [2], 0x400E003C [3], 0x400E004C [4] Access: Read-write – – – – – PMEN – – – TDF_MODE TDF_CYCLES – – – – – – – –...
  • Page 454 • Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
  • Page 455 SAM4S Series [Preliminary] 25.15.5 SMC OCMS Mode Register Name: SMC_OCMS Address: 0x400E0080 Access: Read-write Reset: 0x00000000 – – – – – – – – – – – – CS3SE CS2SE CS1SE CS0SE – – – – – – – – –...
  • Page 456 25.15.7 SMC OCMS Key2 Register Name: SMC_KEY2 Address: 0x400E0088 Access: Write Once Reset: 0x00000000 KEY2 KEY2 KEY2 KEY2 • KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values.
  • Page 457 SAM4S Series [Preliminary] 25.15.8 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0x400E00E4 Access: Read-write Reset: Table 25-6 WPKEY WPKEY WPKEY — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC”...
  • Page 458 25.15.9 SMC Write Protect Status Register Name: SMC_WPSR Address: 0x400E00E8 Type: Read-only Value: Table 25-6 — — — — — — — — WPVSRC WPVSRC — — — — — — — WPVS • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
  • Page 459 SAM4S Series [Preliminary] 26. Peripheral DMA Controller (PDC) 26.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
  • Page 460 Table 26-1. Peripheral DMA Controller Instance Name Channel T/R PIOA Receive TWI1 Receive TWI0 Receive UART1 Receive UART0 Receive USART1 Receive USART0 Receive Receive Receive Receive HSMCI Receive SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 461 SAM4S Series [Preliminary] 26.3 Block Diagram Figure 26-1. Block Diagram FULL DUPLEX PERIPHERAL PDC Channel A PDC Channel B Status & Control Control HALF DUPLEX PERIPHERAL Control PDC Channel C Status & Control Control RECEIVE or TRANSMIT PERIPHERAL PDC Channel D RHR or THR Status &...
  • Page 462 26.4 Functional Description 26.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated periph- eral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
  • Page 463 SAM4S Series [Preliminary] The following list gives an overview of how status register flags behave depending on the coun- ters’ values: • ENDRX flag is set when the PERIPH_RCR register reaches zero. • RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. •...
  • Page 464 26.5 Peripheral DMA Controller (PDC) User Interface Table 26-2. Register Mapping Offset Register Name Access Reset 0x100 Receive Pointer Register PERIPH _RPR Read-write 0x104 Receive Counter Register PERIPH_RCR Read-write 0x108 Transmit Pointer Register PERIPH_TPR Read-write 0x10C Transmit Counter Register PERIPH_TCR Read-write 0x110 Receive Next Pointer Register...
  • Page 465 SAM4S Series [Preliminary] 26.5.1 Receive Pointer Register Name: PERIPH_RPR Access: Read-write RXPTR RXPTR RXPTR RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 11100B–ATARM–31-Jul-12...
  • Page 466 26.5.2 Receive Counter Register Name: PERIPH_RCR Access: Read-write – – – – – – – – – – – – – – – – RXCTR RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the receiver 1 - 65535 = Starts peripheral data transfer if corresponding channel is active SAM4S Series [Preliminary]...
  • Page 467 SAM4S Series [Preliminary] 26.5.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read-write TXPTR TXPTR TXPTR TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 11100B–ATARM–31-Jul-12...
  • Page 468 26.5.4 Transmit Counter Register Name: PERIPH_TCR Access: Read-write – – – – – – – – – – – – – – – – TXCTR TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the transmitter 1- 65535 = Starts peripheral data transfer if corresponding channel is active SAM4S Series [Preliminary]...
  • Page 469 SAM4S Series [Preliminary] 26.5.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read-write RXNPTR RXNPTR RXNPTR RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 11100B–ATARM–31-Jul-12...
  • Page 470 26.5.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read-write – – – – – – – – – – – – – – – – RXNCTR RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 471 SAM4S Series [Preliminary] 26.5.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read-write TXNPTR TXNPTR TXNPTR TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 11100B–ATARM–31-Jul-12...
  • Page 472 26.5.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read-write – – – – – – – – – – – – – – – – TXNCTR TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 473 SAM4S Series [Preliminary] 26.5.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only – – – – – – – – – – – – – – – – – – – – – – TXTDIS TXTEN – – – – – –...
  • Page 474 26.5.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – TXTEN – – – – – – – RXTEN •...
  • Page 475 SAM4S Series [Preliminary] 27. Power Management Controller (PMC) 27.1 Clock Generator 27.1.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 27.2.16 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 27.1.2 Embedded Characteristics The Clock Generator is made up of:...
  • Page 476 27.1.3 Block Diagram Figure 27-1. Clock Generator Block Diagram Clock G ene rator XTALSEL (Supply C ontroller) Embedded 32 kHz RC Oscillator Sl ow Clock SLCK XIN32 32768 Hz Crystal Oscill a tor XOUT32 MOSCSEL Embedded 4/8/12 MHz Fast RC Oscillator Main Clo ck MAINCK 3-20 MHz...
  • Page 477 SAM4S Series [Preliminary] 27.1.4 Slow Clock The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
  • Page 478 the XIN32 pin are given in the product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1. The user can set the Slow Clock Crystal Oscillator in bypass mode instead of connecting a crys- tal.
  • Page 479 The CAL4, CAL8 and CAL12 values in the PMC Oscillator Calibration Register (PMC_OCR) are the default values set by Atmel during production. These values are stored in a specific Flash memory area different from the main memory plane. These values cannot be modified by the user and cannot be erased by a Flash erase command or by the ERASE pin.
  • Page 480 27.1.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator After reset, the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source of MAINCK, as it provides a more accurate frequency.
  • Page 481 SAM4S Series [Preliminary] • when the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set) • when the Main Clock Oscillator selection is modified •...
  • Page 482 27.1.6.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
  • Page 483 SAM4S Series [Preliminary] 27.2 Power Management Controller (PMC) 27.2.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all sys- tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M4 Processor. The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator.
  • Page 484 27.2.3 Block Diagram Figure 27-5. General Clock Block Diagram Clock G ene rator Processor Processor clock c XTALSEL Clock HCLK Controller (Supply C ontroller) Sleep M ode Embedded 32 kH z R C Oscilla tor Divider Sl ow Clock SysTick SLCK Master Clock Controller XIN32...
  • Page 485 SAM4S Series [Preliminary] 27.2.4 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device.
  • Page 486 27.2.7 USB Clock Controller The user can select the PLLA or the PLLB output as the USB Source Clock by writing the USBS bit in PMC_USB. If using the USB, the user must program the PLL to generate an appropriate frequency depending on the USBDIV bit in PMC_USB.
  • Page 487 SAM4S Series [Preliminary] 27.2.10 Programmable Clock Output Controller The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be indepen- dently programmed via the Programmable Clock Registers (PMC_PCKx). PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock (MAINCK), the PLLA Clock (PLLACK), the PLLB Clock (PLLBCK) and the Master Clock (MCK) by writing the CSS field in PMC_PCKx.
  • Page 488 Figure 27-8. Fast Startup Circuitry FSTT0 WKUP0 FSTP0 FSTT1 WKUP1 FSTP1 FSTT15 WKUP15 fast_restart FSTP15 RTTAL RTT Alarm RTCAL RTC Alarm USBAL USB Alarm Each wake-up input pin and alarm can be enabled to generate a Fast Startup event by writing 1 to the corresponding bit in the Fast Startup Mode Register PMC_FSMR.
  • Page 489 SAM4S Series [Preliminary] slow clock RC oscillator clock period. If, during the high level period of the slow clock RC oscilla- tor, less than 8 fast crystal oscillator clock periods have been counted, then a failure is declared. If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not masked.
  • Page 490 The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By default, DIV parameter is set to 0 which means that the divider is turned off. The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 62.
  • Page 491 SAM4S Series [Preliminary] Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock.
  • Page 492 27.2.14 Clock Switching Details 27.2.14.1 Master Clock Switching Timings Table 27-1 Table 27-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added.
  • Page 493 SAM4S Series [Preliminary] 27.2.14.2 Clock Switching Waveforms Figure 27-9. Switch Master Clock from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 27-10. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock...
  • Page 494 Figure 27-11. Change PLLx Programming Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Slow Clock Write CKGR_PLLxR Figure 27-12. Programmable Clock Output Programming PLLx Clock PCKRDY PCKx Output Write PMC_PCKx PLL Clock is selected Write PMC_SCER PCKx is enabled Write PMC_SCDR PCKx is disabled SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 495 SAM4S Series [Preliminary] 27.2.15 Write Protection Registers To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
  • Page 496 27.2.16 Power Management Controller (PMC) User Interface Table 27-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only – 0x0004 System Clock Disable Register PMC_SCDR Write-only – 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0001 0x000C Reserved –...
  • Page 497 SAM4S Series [Preliminary] Table 27-3. Register Mapping Offset Register Name Access Reset 0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000 0x010C Reserved – – – 0x0110 Oscillator Calibration Register PMC_OCR Read-write 0x0040_4040 Note: If an offset is not listed in the table it must be considered as “reserved”. 11100B–ATARM–31-Jul-12...
  • Page 498 27.2.16.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0x400E0400 Access: Write-only – – – – – – – – – – – – – – – – – – – – – PCK2 PCK1 PCK0 – – – – –...
  • Page 499 SAM4S Series [Preliminary] 27.2.16.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0x400E0404 Access: Write-only – – – – – – – – – – – – – – – – – – – – – PCK2 PCK1 PCK0 – –...
  • Page 500 27.2.16.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0x400E0408 Access: Read-only – – – – – – – – – – – – – – – – – – – – – PCK2 PCK1 PCK0 – – – – –...
  • Page 501 SAM4S Series [Preliminary] 27.2.16.4 PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0x400E0410 Access: Write-only PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 PID7 PID6 PID5...
  • Page 502 27.2.16.5 PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0x400E0414 Access: Write-only PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 PID7 PID6 PID5 PID4 PID3 PID2...
  • Page 503 SAM4S Series [Preliminary] 27.2.16.6 PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0x400E0418 Access: Read-only PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 PID7 PID6 PID5...
  • Page 504 27.2.16.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0x400E0420 Access: Read-write – – – – – – CFDEN MOSCSEL MOSCXTST – MOSCRCF MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register”...
  • Page 505 SAM4S Series [Preliminary] • MOSCRCF: Main On-Chip RC Oscillator Frequency Selection At start-up, the Main On-Chip RC Oscillator frequency is 4 MHz. Value Name Description 4_MHz The Fast RC Oscillator Frequency is at 4 MHz (default) 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 12_MHz The Fast RC Oscillator Frequency is at 12 MHz Note:...
  • Page 506 27.2.16.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0x400E0424 Access: Read-Write – – – – – – – – – – – RCMEAS – – – MAINFRDY MAINF MAINF This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register”...
  • Page 507 SAM4S Series [Preliminary] 27.2.16.9 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0x400E0428 Access: Read-write – – – – MULA MULA – – PLLACOUNT DIVA Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
  • Page 508 27.2.16.10 PMC Clock Generator PLLB Register Name: CKGR_PLLBR Address: 0x400E042C Access: Read-write – – – – – MULB MULB – – PLLBCOUNT DIVB Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC. This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register”...
  • Page 509 SAM4S Series [Preliminary] 27.2.16.11 PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0430 Access: Read-write – – – – – – – – – – – – – – – – – – PLLBDIV2 PLLADIV2 – – – – – PRES –...
  • Page 510 • PLLBDIV2: PLLB Divisor by 2 PLLBDIV2 PLLB Clock Division PLLB clock frequency is divided by 1. PLLB clock frequency is divided by 2. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 511 SAM4S Series [Preliminary] 27.2.16.12 PMC USB Clock Register Name: PMC_USB Address: 0x400E0438 Access: Read-write – – – – – – – – – – – – – – – – – – – – USBDIV – – – – – –...
  • Page 512 27.2.16.13 PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0440 Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – – PRES – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register”...
  • Page 513 SAM4S Series [Preliminary] 27.2.16.14 PMC Interrupt Enable Register Name: PMC_IER Address: 0x400E0460 Access: Write-only – – – – – – – – – – – – – CFDEV MOSCRCS MOSCSELS – – – – – PCKRDY2 PCKRDY1 PCKRDY0 – – –...
  • Page 514 27.2.16.15 PMC Interrupt Disable Register Name: PMC_IDR Address: 0x400E0464 Access: Write-only – – – – – – – – – – – – – CFDEV MOSCRCS MOSCSELS – – – – – PCKRDY2 PCKRDY1 PCKRDY0 – – – – MCKRDY LOCKB LOCKA MOSCXTS...
  • Page 515 SAM4S Series [Preliminary] 27.2.16.16 PMC Status Register Name: PMC_SR Address: 0x400E0468 Access: Read-only – – – – – – – – – – – CFDS CFDEV MOSCRCS MOSCSELS – – – – – PCKRDY2 PCKRDY1 PCKRDY0 OSCSELS – – – MCKRDY LOCKB LOCKA...
  • Page 516 1 = Main on-chip RC oscillator is stabilized. • CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. •...
  • Page 517 SAM4S Series [Preliminary] 27.2.16.17 PMC Interrupt Mask Register Name: PMC_IMR Address: 0x400E046C Access: Read-only – – – – – – – – – – – – – CFDEV MOSCRCS MOSCSELS – – – – – PCKRDY2 PCKRDY1 PCKRDY0 – – –...
  • Page 518 27.2.16.18 PMC Fast Startup Mode Register Name: PMC_FSMR Address: 0x400E0470 Access: Read-write – – – – – – – – – FLPM – – USBAL RTCAL RTTAL FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8 FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0...
  • Page 519 SAM4S Series [Preliminary] 27.2.16.19 PMC Fast Startup Polarity Register Name: PMC_FSPR Address: 0x400E0474 Access: Read-write – – – – – – – – – – – – – – – – FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8 FSTP7 FSTP6 FSTP5 FSTP4...
  • Page 520 27.2.16.20 PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0478 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 521 SAM4S Series [Preliminary] 27.2.16.21 PMC Write Protect Mode Register Name: PMC_WPMR Address: 0x400E04E4 Access: Read-write Reset: Table 27-3 WPKEY WPKEY WPKEY – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC”...
  • Page 522 27.2.16.22 PMC Write Protect Status Register Name: PMC_WPSR Address: 0x400E04E8 Access: Read-only Reset: Table 27-3 – – – – – – – – WPVSRC WPVSRC – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register.
  • Page 523 SAM4S Series [Preliminary] 27.2.16.23 PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0x400E0500 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 524 27.2.16.24 PMC Peripheral Clock Disable Register 1 Name: PMC_PCDR1 Address: 0x400E0504 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 525 SAM4S Series [Preliminary] 27.2.16.25 PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0x400E0508 Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 526 27.2.16.26 PMC Oscillator Calibration Register Name: PMC_OCR Address: 0x400E0510 Access: Read-write – – – – – – – – SEL12 CAL12 SEL8 CAL8 SEL4 CAL4 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” •...
  • Page 527 SAM4S Series [Preliminary] 28. Chip Identifier (CHIPID) 28.1 Description The Chip Identifier (CHIPID) registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals.
  • Page 528 Table 28-1. SAM4S Chip IDs Register Flash Size RAM Size Chip Name (KBytes) (KBytes) Pin Count CHIPID_CIDR CHIPID_EXID SAM4SD32C 2*1024 0X29A7_0EE0 SAM4SD32B 2*1024 0X2997_0EE0 SAM4SD16C 2*512 0X29A7_0CE0 SAM4SD16B 2*512 0X2997_0CE0 SAM4SA16C 1024 0X28A7_0CE0 SAM4SA16B 1024 0X2897_0CE0 SAM4S16B 1024 0x289C_0CE0 SAM4S16C...
  • Page 529 SAM4S Series [Preliminary] 28.3 Chip Identifier (CHIPID) User Interface Table 28-2. Register Mapping Offset Register Name Access Reset Chip ID Register CHIPID_CIDR Read-only – Chip ID Extension Register CHIPID_EXID Read-only – 11100B–ATARM–31-Jul-12...
  • Page 530 28.3.1 Chip ID Register Name: CHIPID_CIDR Address: 0x400E0740 Access: Read-only NVPTYP ARCH ARCH SRAMSIZ NVPSIZ2 NVPSIZ EPROC VERSION • VERSION: Version of the Device Current version of the device. • EPROC: Embedded Processor Value Name Description ARM946ES ARM946ES ARM7TDMI ARM7TDMI Cortex-M3 ARM920T ARM920T...
  • Page 531 SAM4S Series [Preliminary] Value Name Description Reserved 2048K 2048K bytes Reserved • NVPSIZ2 Second Nonvolatile Program Memory Size Value Name Description NONE None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K 128K bytes Reserved 256K 256K bytes 512K 512K bytes Reserved...
  • Page 532 Value Name Description 256K 256K bytes 96K bytes 512K 512K bytes • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40...
  • Page 533 SAM4S Series [Preliminary] Value Name Description 0x9A SAM3SDxC SAM3SDxC Series (100-pin version) 0xA5 SAM5A SAM5A 0xF0 AT75Cxx AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type Value Name Description ROMLESS ROMless or on-chip Flash SRAM SRAM emulating ROM FLASH Embedded Flash Memory ROM and Embedded Flash Memory ROM_FLASH NVPSIZ is ROM size...
  • Page 534 28.3.2 Chip ID Extension Register Name: CHIPID_EXID Address: 0x400E0744 Access: Read-only EXID EXID EXID EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in CHIPID_CIDR is 0. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 535 SAM4S Series [Preliminary] 29. Parallel Input/Output Controller (PIO) 29.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral.
  • Page 536 – Can be used to interface a CMOS digital image sensor, an ADC..– One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines – Data Can be Sampled one time of out two (For Chrominance Sampling Only) –...
  • Page 537 SAM4S Series [Preliminary] Table 29-1. Signal Description Signal Name Signal Description Signal Type PIODCCLK Parallel Capture Mode Clock Input PIODC[7:0] Parallel Capture Mode Data Input PIODCEN1 Parallel Capture Mode Data Enable 1 Input PIODCEN2 Parallel Capture Mode Data Enable 2 Input Figure 29-2.
  • Page 538 29.4 Product Dependencies 29.4.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hard- ware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application.
  • Page 539 SAM4S Series [Preliminary] 29.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic asso- ciated to each I/O is represented in Figure 29-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 29-3.
  • Page 540 pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down Enable Register) and PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PPDSR (Pull-down Status Register). Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0 means the pull-down is enabled.
  • Page 541 SAM4S Series [Preliminary] After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the con- figuration of the pin.
  • Page 542 After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 29.5.7 Output Line Timings Figure 29-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set.
  • Page 543 SAM4S Series [Preliminary] Tdiv_slclk = ((DIV+1)*2).Tslow_clock When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted.
  • Page 544 29.5.10 Input Edge/Level Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis- able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register).
  • Page 545 SAM4S Series [Preliminary] Figure 29-7. Event Detector on Input Lines (Figure represents line 0) Event Detector Rising Edge Detector Falling Edge Detector PIO_REHLSR[0] PIO_FRLHSR[0] Event detection on line 0 PIO_FELLSR[0] Resynchronized input on line 0 High Level Detector Low Level Detector PIO_LSR[0] PIO_ELSR[0]...
  • Page 546 The other lines are configured in Falling Edge or Low Level detection by default, if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing 32’h0000_004A in PIO_FELLSR. Figure 29-8.
  • Page 547 SAM4S Series [Preliminary] Figure 29-9. PIO controller connection with CMOS digital image sensor PIO Controller Parallel Capture CMOS Digital Mode Image Sensor PCLK PIODCCLK Data DATA[7:0] PIODC[7:0] Status VSYNC PIODCEN1 HSYNC PIODCEN2 As soon as the parallel capture mode is enabled by writing the PCEN bit at 1 in PIO_PCMR (“PIO Parallel Capture Mode Register”...
  • Page 548 PIO_PCRHR and it is not read before a new data is stored in PIO_PCRHR, then an overrun error occurs. The previous data is lost and the OVRE flag in PIO_PCISR is set to 1. This flag is automatically reset when PIO_PCISR is read (reset after read). The flags DRDY, OVRE, ENDRX and RXBUFF can be a source of the PIO interrupt.
  • Page 549 SAM4S Series [Preliminary] Figure 29-12. Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=0) PIODCCLK 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODC[7:0] PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR 0x6745_2301 RDATA (PIO_PCRHR) Figure 29-13. Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=1) PIODCCLK 0x01 0x12...
  • Page 550 29.5.13.3 Restrictions • Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR (“PIO Parallel Capture Mode Register” ) can be changed ONLY if the parallel capture mode is disabled at this time (PCEN = 0 in PIO_PCMR). • Frequency of PIO controller clock must be strictly superior to 2 times the frequency of the clock of the device which generates the parallel data.
  • Page 551 SAM4S Series [Preliminary] 29.5.14 Write Protection Registers To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Pro- tect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
  • Page 552 29.6 I/O Lines Programming Example The programing example as shown in Table 29-2 below is used to obtain the following configuration. • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor •...
  • Page 553 SAM4S Series [Preliminary] 29.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control- ler User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect.
  • Page 554 Table 29-3. Register Mapping (Continued) Offset Register Name Access Reset 0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read-write 0x00000000 0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read-write 0x00000000 0x0078 Reserved 0x007C 0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only – 0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only...
  • Page 555 SAM4S Series [Preliminary] Table 29-3. Register Mapping (Continued) Offset Register Name Access Reset 0x0110 Reserved 0x0114- Reserved 0x011C 0x150 Parallel Capture Mode Register PIO_PCMR Read-write 0x00000000 0x154 Parallel Capture Interrupt Enable Register PIO_PCIER Write-only – 0x158 Parallel Capture Interrupt Disable Register PIO_PCIDR Write-only –...
  • Page 556 29.7.1 PIO Enable Register Name: PIO_PER Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
  • Page 557 SAM4S Series [Preliminary] 29.7.3 PIO Status Register Name: PIO_PSR Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC) Access: Read-only • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). 29.7.4 PIO Output Enable Register Name:...
  • Page 558 29.7.5 PIO Output Disable Register Name: PIO_ODR Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line.
  • Page 559 SAM4S Series [Preliminary] 29.7.7 PIO Input Filter Enable Register Name: PIO_IFER Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Input Filter Enable 0 = No effect.
  • Page 560 29.7.9 PIO Input Filter Status Register Name: PIO_IFSR Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC) Access: Read-only • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 29.7.10 PIO Set Output Data Register Name:...
  • Page 561 SAM4S Series [Preliminary] 29.7.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC) Access: Write-only • P0-P31: Clear Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 29.7.12 PIO Output Data Status Register Name:...
  • Page 562 29.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC) Access: Read-only • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 29.7.14 PIO Interrupt Enable Register Name:...
  • Page 563 SAM4S Series [Preliminary] 29.7.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC) Access: Write-only • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 29.7.16 PIO Interrupt Mask Register Name:...
  • Page 564 29.7.17 PIO Interrupt Status Register Name: PIO_ISR Address: 0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC) Access: Read-only • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
  • Page 565 SAM4S Series [Preliminary] 29.7.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x400E1254 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Multi Drive Disable. 0 = No effect.
  • Page 566 29.7.21 PIO Pull Up Disable Register Name: PIO_PUDR Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Pull Up Disable. 0 = No effect.
  • Page 567 SAM4S Series [Preliminary] 29.7.23 PIO Pull Up Status Register Name: PIO_PUSR Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC) Access: Read-only • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 11100B–ATARM–31-Jul-12...
  • Page 568 29.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read-write This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Peripheral Select. If the same bit is set to 0 in PIO_ABCDSR2: 0 = Assigns the I/O line to the Peripheral A function.
  • Page 569 SAM4S Series [Preliminary] 29.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read-write This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Peripheral Select. If the same bit is set to 0 in PIO_ABCDSR1: 0 = Assigns the I/O line to the Peripheral A function.
  • Page 570 29.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC) Access: Write-only • P0-P31: PIO Clock Glitch Filtering Select. 0 = No Effect. 1 = The Glitch Filter is able to filter glitches with a duration < Tmck/2. 29.7.27 PIO Input Filter Slow Clock Enable Register Name:...
  • Page 571 SAM4S Series [Preliminary] 29.7.28 PIO Input Filter Slow Clock Status Register Name: PIO_IFSCSR Address: 0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC) Access: Read-only • P0-P31: Glitch or Debouncing Filter Selection Status 0 = The Glitch Filter is able to filter glitches with a duration < Tmck2. 1 = The Debouncing Filter is able to filter pulses with a duration <...
  • Page 572 29.7.30 PIO Pad Pull Down Disable Register Name: PIO_PPDDR Address: 0x400E0E90 (PIOA), 0x400E1090 (PIOB), 0x400E1290 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Pull Down Disable. 0 = No effect.
  • Page 573 SAM4S Series [Preliminary] 29.7.32 PIO Pad Pull Down Status Register Name: PIO_PPDSR Address: 0x400E0E98 (PIOA), 0x400E1098 (PIOB), 0x400E1298 (PIOC) Access: Read-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Pull Down Status. 0 = Pull Down resistor is enabled on the I/O line.
  • Page 574 29.7.33 PIO Output Write Enable Register Name: PIO_OWER Address: 0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x400E12A0 (PIOC) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” • P0-P31: Output Write Enable. 0 = No effect.
  • Page 575 SAM4S Series [Preliminary] 29.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC) Access: Read-only • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 29.7.36 PIO Additional Interrupt Modes Enable Register Name:...
  • Page 576 29.7.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC) Access: Write-only • P0-P31: Additional Interrupt Modes Disable. 0 = No effect. 1 = The interrupt mode is set to the default interrupt mode (Both Edge detection). 29.7.38 PIO Additional Interrupt Modes Mask Register Name:...
  • Page 577 SAM4S Series [Preliminary] 29.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC) Access: Write-only • P0-P31: Edge Interrupt Selection. 0 = No effect. 1 = The interrupt source is an Edge detection event. 29.7.40 PIO Level Select Register Name: PIO_LSR Address:...
  • Page 578 29.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC) Access: Read-only • P0-P31: Edge/Level Interrupt source selection. 0 = The interrupt source is an Edge detection event. 1 = The interrupt source is a Level detection event. 29.7.42 PIO Falling Edge/Low Level Select Register Name:...
  • Page 579 SAM4S Series [Preliminary] 29.7.43 PIO Rising Edge/High Level Select Register Name: PIO_REHLSR Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC) Access: Write-only • P0-P31: Rising Edge /High Level Interrupt Selection. 0 = No effect. 1 = The interrupt source is set to a Rising Edge detection or High Level detection event, depending on PIO_ELSR. 29.7.44 PIO Fall/Rise - Low/High Status Register Name:...
  • Page 580 29.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC) Access: Read-only • P0-P31: Lock Status. 0 = The I/O line is not locked. 1 = The I/O line is locked. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 581 SAM4S Series [Preliminary] 29.7.46 PIO Write Protect Mode Register Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC) Access: Read-write Reset: Table 29-3 WPKEY WPKEY WPKEY WPEN – – – – – – – For more information on Write Protection Registers, refer to Section 29.7 ”Parallel Input/Output Controller (PIO) User Interface”.
  • Page 582 29.7.47 PIO Write Protect Status Register Name: PIO_WPSR Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC) Access: Read-only Reset: Table 29-3 – – – – – – – – WPVSRC WPVSRC WPVS – – – – – – – • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
  • Page 583 SAM4S Series [Preliminary] 29.7.48 PIO Schmitt Trigger Register Name: PIO_SCHMITT Address: 0x400E0F00 (PIOA), 0x400E1100 (PIOB), 0x400E1300 (PIOC) Access: Read-write Reset: Figure 29-3 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11...
  • Page 584 29.7.49 PIO Parallel Capture Mode Register Name: PIO_PCMR Address: 0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC) Access: Read-write – – – – – – – – – – – – – – – – – – – – FRSTS HALFS ALWYS –...
  • Page 585 SAM4S Series [Preliminary] 29.7.50 PIO Parallel Capture Interrupt Enable Register Name: PIO_PCIER Address: 0x400E0F54 (PIOA), 0x400E1154 (PIOB), 0x400E1354 (PIOC) Access: Write-only – – – – – – – – – – – – – – – – – – – –...
  • Page 586 29.7.52 PIO Parallel Capture Interrupt Mask Register Name: PIO_PCIMR Address: 0x400E0F5C (PIOA), 0x400E115C (PIOB), 0x400E135C (PIOC) Access: Read-only – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 587 SAM4S Series [Preliminary] 29.7.53 PIO Parallel Capture Interrupt Status Register Name: PIO_PCISR Address: 0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC) Access: Read-only – – – – – – – – – – – – – – – – – – – –...
  • Page 588 29.7.54 PIO Parallel Capture Reception Holding Register Name: PIO_PCRHR Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC) Access: Read-only RDATA RDATA RDATA RDATA • RDATA: Parallel Capture Mode Reception Data. If DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful. If DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful.
  • Page 589 30.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
  • Page 590 30.3 Block Diagram Figure 30-1. Block Diagram System APB Bridge Peripheral SSC Interface Interrupt Control SSC Interrupt 30.4 Application Block Diagram Figure 30-2. Application Block Diagram Power Interrupt Test OS or RTOS Driver Management Management Management Time Slot Frame Serial AUDIO Codec Line Interface Management...
  • Page 591 SAM4S Series [Preliminary] 30.5 Pin Name List Table 30-1. I/O Lines Description Pin Name Pin Description Type Receiver Frame Synchro Input/Output Receiver Clock Input/Output Receiver Data Input Transmitter Frame Synchro Input/Output Transmitter Clock Input/Output Transmitter Data Output 30.6 Product Dependencies 30.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
  • Page 592 30.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by pro- gramming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
  • Page 593 SAM4S Series [Preliminary] The receiver clock can be generated by: • An external clock received on the RK I/O pad • The transmitter clock • The internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
  • Page 594 Table 30-4. Maximum Minimum MCK / 2 MCK / 8190 30.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register).
  • Page 595 SAM4S Series [Preliminary] Figure 30-7. Receiver Clock Management RK (pin) Tri-state Clock Controller Output Transmitter Clock Divider Clock Data Transfer Tri-state Receiver Controller Clock 30.7.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins.
  • Page 596 Figure 30-8. Transmitter Block Diagram SSC_CRTXEN TXEN SSC_SRTXEN SSC_CRTXDIS SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB SSC_RCMR.START SSC_TCMR.START SSC_TFMR.DATDEF TX Controller SSC_TFMR.MSBF RXEN TXEN TX Start TX Start Start RX Start Start Selector Selector RC0R Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY != 0 Transmitter Clock SSC_TFMR.DATLEN SSC_TFMR.FSLEN SSC_THR...
  • Page 597 SAM4S Series [Preliminary] Figure 30-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START SSC_RFMR.MSBF TXEN SSC_RFMR.DATNB RXEN RX Start Start RX Start Start RX Controller Selector Selector RC0R Receive Shift Register SSC_RCMR.STTDLY != 0 Receiver Clock SSC_RSHR SSC_RHR load load SSC_RFMR.FSLEN SSC_RFMR.DATLEN RX Controller counter reached STTDLY...
  • Page 598 Figure 30-10. Transmit Start Mode (Input) Start = Low Level on TF (Output) STTDLY Start = Falling Edge on TF (Output) STTDLY Start = High Level on TF STTDLY (Output) Start = Rising Edge on TF (Output) STTDLY Start = Level Change on TF (Output) STTDLY Start = Any Edge on TF...
  • Page 599 SAM4S Series [Preliminary] 30.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.
  • Page 600 30.7.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver.
  • Page 601 SAM4S Series [Preliminary] Table 30-5. Data Frame Registers Transmitter Receiver Field Length Comment SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame SSC_TFMR SSC_RFMR MSBF Most significant bit first SSC_TFMR SSC_RFMR FSLEN...
  • Page 602 Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 30-15. Receive Frame Format in Continuous Mode Start = Enable Receiver Data Data To SSC_RHR...
  • Page 603 SAM4S Series [Preliminary] 30.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 30-17.
  • Page 604 Figure 30-19. Time Slot Application Block Diagram SCLK FSYNC CODEC First Data Out Time Slot Data in CODEC Second Time Slot Serial Data Clock (SCLK) First Time Slot Second Time Slot Frame sync (FSYNC) Dstart Dend Serial Data Out Serial Data in SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 605 SAM4S Series [Preliminary] 30.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Pro- tect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
  • Page 606 30.9 Synchronous Serial Controller (SSC) User Interface Table 30-6. Register Mapping Offset Register Name Access Reset Control Register SSC_CR Write-only – Clock Mode Register SSC_CMR Read-write Reserved – – – Reserved – – – 0x10 Receive Clock Mode Register SSC_RCMR Read-write 0x14 Receive Frame Mode Register...
  • Page 607 SAM4S Series [Preliminary] 30.9.1 SSC Control Register Name: SSC_CR: Address: 0x40004000 Access: Write-only – – – – – – – – – – – – – – – – SWRST – – – – – TXDIS TXEN – – – –...
  • Page 608 30.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0x40004004 Access: Read-write – – – – – – – – – – – – – – – – – – – – This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register”...
  • Page 609 SAM4S Series [Preliminary] 30.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0x40004010 Access: Read-write PERIOD STTDLY – – – STOP START This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” •...
  • Page 610 • CKG: Receive Clock Gating Selection Value Name Description RK Pin NONE None Input-only CONTINUOUS Continuous Receive Clock Output TRANSFER Receive Clock only during data transfers Output Reserved • START: Receive Start Selection Value Name Description Continuous, as soon as the receiver is enabled, and CONTINUOUS immediately after the end of transfer of the previous data.
  • Page 611 SAM4S Series [Preliminary] 30.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0x40004014 Access: Read-write FSLEN_EXT FSLEN_EXT FSLEN_EXT – – – FSEDGE FSLEN_EXT – FSOS FSLEN – – – – DATNB MSBF – LOOP DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register”...
  • Page 612 • FSOS: Receive Frame Sync Output Selection Value Name Description RF Pin NONE None Input-only NEGATIVE Negative Pulse Output POSITIVE Positive Pulse Output Driven Low during data transfer Output HIGH Driven High during data transfer Output TOGGLING Toggling at each start of data transfer Output Reserved Undefined...
  • Page 613 SAM4S Series [Preliminary] 30.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0x40004018 Access: Read-write PERIOD STTDLY – – – – START This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” •...
  • Page 614 • CKG: Transmit Clock Gating Selection Value Name Description NONE None CONTINUOUS Transmit Clock enabled only if TF Low TRANSFER Transmit Clock enabled only if TF High • START: Transmit Start Selection Value Name Description Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and CONTINUOUS immediately after the end of transfer of the previous data.
  • Page 615 SAM4S Series [Preliminary] 30.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0x4000401C Access: Read-write FSLEN_EXT FSLEN_EXT FSLEN_EXT – – – FSEDGE FSLEN_EXT FSDEN FSOS FSLEN – – – – DATNB MSBF – DATDEF DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register”...
  • Page 616 • FSOS: Transmit Frame Sync Output Selection Value Name Description RF Pin NONE None Input-only NEGATIVE Negative Pulse Output POSITIVE Positive Pulse Output Driven Low during data transfer Output HIGH Driven High during data transfer Output TOGGLING Toggling at each start of data transfer Output Reserved Undefined...
  • Page 617 SAM4S Series [Preliminary] 30.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0x40004020 Access: Read-only RDAT RDAT RDAT RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 11100B–ATARM–31-Jul-12...
  • Page 618 30.9.8 SSC Transmit Holding Register Name: SSC_THR Address: 0x40004024 Access: Write-only TDAT TDAT TDAT TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 619 SAM4S Series [Preliminary] 30.9.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Address: 0x40004030 Access: Read-only – – – – – – – – – – – – – – – – RSDAT RSDAT • RSDAT: Receive Synchronization Data 11100B–ATARM–31-Jul-12...
  • Page 620 30.9.10 SSC Transmit Synchronization Holding Register Name: SSC_TSHR Address: 0x40004034 Access: Read-write – – – – – – – – – – – – – – – – TSDAT TSDAT • TSDAT: Transmit Synchronization Data SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 621 SAM4S Series [Preliminary] 30.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0x40004038 Access: Read-write – – – – – – – – – – – – – – – – This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register”...
  • Page 622 30.9.12 SSC Receive Compare 1 Register Name: SSC_RC1R Address: 0x4000403C Access: Read-write – – – – – – – – – – – – – – – – This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register”...
  • Page 623 SAM4S Series [Preliminary] 30.9.13 SSC Status Register Name: SSC_SR Address: 0x40004040 Access: Read-only – – – – – – – – – – – – – – RXEN TXEN – – – – RXSYN TXSYN RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY...
  • Page 624 • RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register.
  • Page 625 SAM4S Series [Preliminary] 30.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0x40004044 Access: Write-only – – – – – – – – – – – – – – – – – – – – RXSYN TXSYN RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY...
  • Page 626 • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect.
  • Page 627 SAM4S Series [Preliminary] 30.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0x40004048 Access: Write-only – – – – – – – – – – – – – – – – – – – – RXSYN TXSYN RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY...
  • Page 628 • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect.
  • Page 629 SAM4S Series [Preliminary] 30.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0x4000404C Access: Read-only – – – – – – – – – – – – – – – – – – – – RXSYN TXSYN RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY...
  • Page 630 • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. •...
  • Page 631 SAM4S Series [Preliminary] 30.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0x400040E4 Access: Read-write Reset: Table 30-6 WPKEY WPKEY WPKEY — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC”...
  • Page 632 30.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0x400040E8 Access: Read-only Reset: Table 30-6 — — — — — — — — WPVSRC WPVSRC — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the SSC_WPSR register.
  • Page 633 SAM4S Series [Preliminary] 31. Serial Peripheral Interface (SPI) 31.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com- munication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
  • Page 634 31.3 Block Diagram Figure 31-1. Block Diagram SPCK MISO MOSI SPI Interface NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 31.4 Application Block Diagram Figure 31-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK SPCK MISO MISO Slave 0 MOSI MOSI SPI Master NPCS0...
  • Page 635 SAM4S Series [Preliminary] 31.5 Signal Description Signal Description Type Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output...
  • Page 636 31.6 Product Dependencies 31.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 31-1. I/O Lines Instance Signal...
  • Page 637 SAM4S Series [Preliminary] 31.7 Functional Description 31.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter.
  • Page 638 Figure 31-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) (to slave) * Not defined, but normally MSB of previous character received. Figure 31-4.
  • Page 639 SAM4S Series [Preliminary] 31.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal pro- grammable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).
  • Page 640 31.7.3.1 Master Mode Block Diagram Figure 31-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator SPCK Clock SPI_CSR0..3 SPI_RDR RDRF BITS OVRES NCPHA CPOL Shift Register MOSI MISO SPI_TDR TDRE SPI_CSR0..3 SPI_RDR CSAAT NPCS3 PCSDEC SPI_MR Current NPCS2 Peripheral NPCS1 SPI_TDR NPCS0...
  • Page 641 SAM4S Series [Preliminary] 31.7.3.2 Master Mode Flow Diagram Figure 31-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
  • Page 642 Figure 31-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg- ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 31-7.
  • Page 643 SAM4S Series [Preliminary] Figure 31-8. PDC Status Register Flags Behavior SPCK NPCS0 MOSI (from master) MISO (from slave) ENDTX ENDRX TXBUFE RXBUFF TXEMPTY 31.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
  • Page 644 These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 31-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 31.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
  • Page 645 SAM4S Series [Preliminary] 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro- gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to.
  • Page 646 PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure 31-10 below shows such an implementation.
  • Page 647 SAM4S Series [Preliminary] 31.7.3.9 Peripheral Deselection with PDC When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE flag is set to one.
  • Page 648 Figure 31-11. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 CSAAT = 1 and CSNAAT= 0 / 1 TDRE DLYBCT DLYBCT NPCS[0..3] DLYBCS DLYBCS PCS = A PCS = A Write SPI_TDR TDRE DLYBCT DLYBCT NPCS[0..3] DLYBCS DLYBCS PCS=A PCS = A Write SPI_TDR TDRE...
  • Page 649 SAM4S Series [Preliminary] By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 31.7.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
  • Page 650 Figure 31-12 shows a block diagram of the SPI when operating in Slave Mode. Figure 31-12. Slave Mode Functional Bloc Diagram SPCK Clock SPIEN SPIENS SPIDIS SPI_CSR0 SPI_RDR RDRF BITS OVRES NCPHA CPOL Shift Register MISO MOSI SPI_TDR TDRE 31.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register...
  • Page 651 SAM4S Series [Preliminary] 31.8 Serial Peripheral Interface (SPI) User Interface Table 31-4. Register Mapping Offset Register Name Access Reset 0x00 Control Register SPI_CR Write-only 0x04 Mode Register SPI_MR Read-write 0x08 Receive Data Register SPI_RDR Read-only 0x0C Transmit Data Register SPI_TDR Write-only 0x10 Status Register...
  • Page 652 31.8.1 SPI Control Register Name: SPI_CR Address: 0x40008000 Access: Write-only – – – – – – – LASTXFER – – – – – – – – – – – – – – – – SWRST – – – – – SPIDIS SPIEN •...
  • Page 653 SAM4S Series [Preliminary] 31.8.2 SPI Mode Register Name: SPI_MR Address: 0x40008004 Access: Read-write DLYBCS – – – – – – – – – – – – – WDRBT MODFDIS – PCSDEC MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”.
  • Page 654 • LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
  • Page 655 SAM4S Series [Preliminary] 31.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0x40008008 Access: Read-only – – – – – – – – – – – – • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. •...
  • Page 656 31.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0x4000800C Access: Write-only – – – – – – – LASTXFER – – – – • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
  • Page 657 SAM4S Series [Preliminary] 31.8.5 SPI Status Register Name: SPI_SR Address: 0x40008010 Access: Read-only – – – – – – – – – – – – – – – SPIENS – – – – – UNDES TXEMPTY NSSR TXBUFE RXBUFF ENDTX ENDRX OVRES MODF...
  • Page 658 • TXBUFE: TX Buffer Empty 0 = SPI_TCR or SPI_TNCR has a value other than 0. 1 = Both SPI_TCR and SPI_TNCR have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read.
  • Page 659 SAM4S Series [Preliminary] 31.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0x40008014 Access: Write-only – – – – – – – – – – – – – – – – – – – – – UNDES TXEMPTY NSSR TXBUFE RXBUFF ENDTX ENDRX OVRES...
  • Page 660 31.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0x40008018 Access: Write-only – – – – – – – – – – – – – – – – – – – – – UNDES TXEMPTY NSSR TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF...
  • Page 661 SAM4S Series [Preliminary] 31.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0x4000801C Access: Read-only – – – – – – – – – – – – – – – – – – – – – UNDES TXEMPTY NSSR TXBUFE RXBUFF ENDTX ENDRX OVRES...
  • Page 662 31.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0x40008030 Access: Read/Write DLYBCT DLYBS SCBR BITS CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans- lated value unless the register is written.
  • Page 663 SAM4S Series [Preliminary] • BITS: Bits Per Transfer (Note:) (See the below the register table; Section 31.8.9 “SPI Chip Select Register” on page 662.) The BITS field determines the number of data bits transferred. Reserved values should not be used. Value Name Description...
  • Page 664 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
  • Page 665 SAM4S Series [Preliminary] 31.8.10 SPI Write Protection Mode Register Name: SPI_WPMR Address: 0x400080E4 Access: Read-write WPKEY WPKEY WPKEY WPEN • WPEN: Write Protection Enable 0: The Write Protection is Disabled 1: The Write Protection is Enabled • WPKEY: Write Protection Key Password If a value is written in WPEN, the value is taken into account only if WPKEY is written with “SPI”...
  • Page 666 31.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0x400080E8 Access: Read-only – – – – – – – – – – – – – – – – WPVSRC WPVS – – – – – – – • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
  • Page 667 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
  • Page 668 32.3 List of Abbreviations Table 32-2. Abbreviations Abbreviation Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start SADR Slave Address Any address except SADR Read Write 32.4 Block Diagram Figure 32-1. Block Diagram APB Bridge TWCK Two-wire Interface Interrupt NVIC SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 669 SAM4S Series [Preliminary] 32.5 Application Block Diagram Figure 32-2. Application Block Diagram Host with TWCK Interface Atmel TWI I²C LCD I²C Temp. I²C RTC Serial EEPROM Controller Sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 32.5.1...
  • Page 670 32.6 Product Dependencies 32.6.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 32-2 on page 669). When the bus is free, both lines are high.
  • Page 671 SAM4S Series [Preliminary] 32.7 Functional Description 32.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 32-4).
  • Page 672 The Master is the device that starts a transfer, generates a clock and stops it. 32.8.2 Application Block Diagram Figure 32-5. Master Mode Typical Application Block Diagram Host with TWCK Interface Atmel TWI I²C LCD I²C Temp. I²C RTC Serial EEPROM Controller Sensor...
  • Page 673 SAM4S Series [Preliminary] While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing in the STOP field of TWI_CR.
  • Page 674 Figure 32-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) DADR IADR DATA n DATA n+1 DATA n+2 TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 32.8.5...
  • Page 675 SAM4S Series [Preliminary] Figure 32-10. Master Read with Multiple Data Bytes DADR DATA n DATA (n+1) DATA (n+m)-1 DATA (n+m) TXCOMP Write START Bit RXRDY Read RHR Read RHR Read RHR Read RHR DATA n DATA (n+1) DATA (n+m)-1 DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel.
  • Page 676 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 32-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 32-13. Internal Address Usage...
  • Page 677 SAM4S Series [Preliminary] 32.8.7 Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: 32.8.7.1 Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2.
  • Page 678 32.8.9 Read-write Flowcharts The following flowcharts shown in Figure 32-16 on page 679, Figure 32-17 on page 680, Figure 32-18 on page 681, Figure 32-19 on page 682 Figure 32-20 on page 683 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
  • Page 679 SAM4S Series [Preliminary] Figure 32-16. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit...
  • Page 680 Figure 32-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used)
  • Page 681 SAM4S Series [Preliminary] Figure 32-18. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==>...
  • Page 682 Figure 32-19. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit...
  • Page 683 SAM4S Series [Preliminary] Figure 32-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used)
  • Page 684 32.9 Multi-master Mode 32.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero.
  • Page 685 SAM4S Series [Preliminary] Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.
  • Page 686 Figure 32-23. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? SVREAD = 0 ? EOSACC = 1 ? TXRDY= 1 ? Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? Read TWI_RHR a master access ?
  • Page 687 SAM4S Series [Preliminary] 32.10 Slave Mode 32.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master).
  • Page 688 Note that a STOP or a repeated START always follows a NACK. Figure 32-25 on page 689. 32.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register).
  • Page 689 SAM4S Series [Preliminary] Figure 32-25. Read Access Ordered by a MASTER SADR matches, SADR does not match, TWI answers with an ACK TWI answers with a NACK ACK/NACK from the Master DATA P/S/Sr SADR DATA DATA S/Sr TXRDY Read RHR Write THR NACK SVACC...
  • Page 690 32.10.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards.
  • Page 691 SAM4S Series [Preliminary] 32.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emp- tied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected.
  • Page 692 Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 32-29 on page 692 describes the clock synchronization in Read mode.
  • Page 693 SAM4S Series [Preliminary] 32.10.5.5 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 32-30 on page 693 describes the repeated start + reversal from Read to Write mode. Figure 32-30.
  • Page 694 32.10.6 Read Write Flowcharts The flowchart shown in Figure 32-32 on page 694 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 32-32.
  • Page 695 SAM4S Series [Preliminary] 32.11 Two-wire Interface (TWI) User Interface Table 32-6. Register Mapping Offset Register Name Access Reset 0x00 Control Register TWI_CR Write-only N / A 0x04 Master Mode Register TWI_MMR Read-write 0x00000000 0x08 Slave Mode Register TWI_SMR Read-write 0x00000000 0x0C Internal Address Register TWI_IADR...
  • Page 696 32.11.1 TWI Control Register Name: TWI_CR Address: 0x40018000 (0), 0x4001C000 (1) Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – SWRST QUICK SVDIS SVEN...
  • Page 697 SAM4S Series [Preliminary] • SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect.
  • Page 698 32.11.2 TWI Master Mode Register Name: TWI_MMR Address: 0x40018004 (0), 0x4001C004 (1) Access: Read-write Reset: 0x00000000 – – – – – – – – – DADR – – – MREAD – – IADRSZ – – – – – – – –...
  • Page 699 SAM4S Series [Preliminary] 32.11.3 TWI Slave Mode Register Name: TWI_SMR Address: 0x40018008 (0), 0x4001C008 (1) Access: Read-write Reset: 0x00000000 – – – – – – – – – SADR – – – – – – – – – – – –...
  • Page 700 32.11.4 TWI Internal Address Register Name: TWI_IADR Address: 0x4001800C (0), 0x4001C00C (1) Access: Read-write Reset: 0x00000000 – – – – – – – – IADR IADR IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 701 SAM4S Series [Preliminary] 32.11.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0x40018010 (0), 0x4001C010 (1) Access: Read-write Reset: 0x00000000 – – – – – – – – CKDIV CHDIV CLDIV TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The SCL low period is defined as follows: CKDIV ×...
  • Page 702 32.11.6 TWI Status Register Name: TWI_SR Address: 0x40018020 (0), 0x4001C020 (1) Access: Read-only Reset: 0x0000F009 – – – – – – – – – – – – – – – – TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK – OVRE GACC SVACC...
  • Page 703 SAM4S Series [Preliminary] TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped.
  • Page 704 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI.
  • Page 705 SAM4S Series [Preliminary] 32.11.7 TWI Interrupt Enable Register Name: TWI_IER Address: 0x40018024 (0), 0x4001C024 (1) Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK...
  • Page 706 32.11.8 TWI Interrupt Disable Register Name: TWI_IDR Address: 0x40018028 (0), 0x4001C028 (1) Access: Write-only Reset: 0x00000000 – – – – – – – – – – – – – – – – TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK –...
  • Page 707 SAM4S Series [Preliminary] 32.11.9 TWI Interrupt Mask Register Name: TWI_IMR Address: 0x4001802C (0), 0x4001C02C (1) Access: Read-only Reset: 0x00000000 – – – – – – – – – – – – – – – – TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK...
  • Page 708 32.11.10 TWI Receive Holding Register Name: TWI_RHR Address: 0x40018030 (0), 0x4001C030 (1) Access: Read-only Reset: 0x00000000 – – – – – – – – – – – – – – – – – – – – – – – – RXDATA •...
  • Page 709 SAM4S Series [Preliminary] 33. Universal Asynchronous Receiver Transmitter (UART) 33.1 Description The Universal Asynchronous Receiver Transmitter (UART) features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with two peripheral DMA controller (PDC) channels permits packet handling for these tasks with processor time reduced to a minimum.
  • Page 710 33.3 Block Diagram Figure 33-1. UART Functional Block Diagram Peripheral Bridge Peripheral DMA Controller UART UTXD Transmit Power Parallel Baud Rate Management Input/ Generator Controller Output Receive URXD Interrupt uart_irq Control Table 33-1. UART Pin Description Pin Name Description Type URXD UART Receive Data Input...
  • Page 711 SAM4S Series [Preliminary] 33.4 Product Dependencies 33.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The programmer must first configure the corre- sponding PIO Controller to enable I/O line operations of the UART. Table 33-2. I/O Lines Instance Signal I/O Line Peripheral...
  • Page 712 Figure 33-2. Baud Rate Generator 16-bit Counter >1 Divide Baud Rate by 16 Clock Receiver Sampling Clock 33.5.2 Receiver 33.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1.
  • Page 713 SAM4S Series [Preliminary] Figure 33-3. Start Bit Detection Sampling Clock URXD True Start Detection Baud Rate Clock Figure 33-4. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit 1 bit period period URXD Sampling Stop Bit True Start Detection Parity Bit 33.5.2.3 Receiver Ready...
  • Page 714 Figure 33-6. Receiver Overrun stop URXD stop RXRDY OVRE RSTSTA 33.5.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in UART_MR. It then compares the result with the received parity bit.
  • Page 715 SAM4S Series [Preliminary] 33.5.3 Transmitter 33.5.3.1 Transmitter Reset, Enable and Disable After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
  • Page 716 Figure 33-10. Transmitter Control UART_THR Data 0 Data 1 Shift Register Data 0 Data 1 UTXD Data 0 stop Data 1 stop TXRDY TXEMPTY Write Data 0 Write Data 1 in UART_THR in UART_THR 33.5.4 Peripheral DMA Controller Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel.
  • Page 717 SAM4S Series [Preliminary] Figure 33-11. Test Modes Automatic Echo Receiver Disabled Transmitter Local Loopback Disabled Receiver Disabled Transmitter Remote Loopback Disabled Receiver Disabled Transmitter 11100B–ATARM–31-Jul-12...
  • Page 718 33.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 33-3. Register Mapping Offset Register Name Access Reset 0x0000 Control Register UART_CR Write-only – 0x0004 Mode Register UART_MR Read-write 0x0008 Interrupt Enable Register UART_IER Write-only – 0x000C Interrupt Disable Register UART_IDR Write-only –...
  • Page 719 SAM4S Series [Preliminary] 33.6.1 UART Control Register Name: UART_CR Address: 0x400E0600 (0), 0x400E0800 (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – RSTSTA –...
  • Page 720 33.6.2 UART Mode Register Name: UART_MR Address: 0x400E0604 (0), 0x400E0804 (1) Access: Read-write – – – – – – – – – – – – – – – – – – – CHMODE – – – – – – – –...
  • Page 721 SAM4S Series [Preliminary] 33.6.3 UART Interrupt Enable Register Name: UART_IER Address: 0x400E0608 (0), 0x400E0808 (1) Access: Write-only – – – – – – – – – – – – – – – – – – – RXBUFF TXBUFE – TXEMPTY –...
  • Page 722 33.6.4 UART Interrupt Disable Register Name: UART_IDR Address: 0x400E060C (0), 0x400E080C (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – RXBUFF TXBUFE TXEMPTY – PARE FRAME OVRE ENDTX...
  • Page 723 SAM4S Series [Preliminary] 33.6.5 UART Interrupt Mask Register Name: UART_IMR Address: 0x400E0610 (0), 0x400E0810 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – RXBUFF TXBUFE – TXEMPTY –...
  • Page 724 33.6.6 UART Status Register Name: UART_SR Address: 0x400E0614 (0), 0x400E0814 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – RXBUFF TXBUFE TXEMPTY – PARE FRAME OVRE ENDTX ENDRX...
  • Page 725 SAM4S Series [Preliminary] • TXEMPTY: Transmitter Empty 0 = There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in UART_THR and there are no characters being processed by the transmitter. •...
  • Page 726 33.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0x400E0618 (0), 0x400E0818 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
  • Page 727 SAM4S Series [Preliminary] 33.6.8 UART Transmit Holding Register Name: UART_THR Address: 0x400E061C (0), 0x400E081C (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 728 33.6.9 UART Baud Rate Generator Register Name: UART_BRGR Address: 0x400E0620 (0), 0x400E0820 (1) Access: Read-write – – – – – – – – – – – – – – – – • CD: Clock Divisor Baud Rate Clock is disabled 1 to 65,535 = MCK / (CD x 16) SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 729 SAM4S Series [Preliminary] 34. Universal Synchronous Asynchronous Receiver Transmitter (USART) 34.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
  • Page 730 • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 34.3 Block Diagram Figure 34-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel USART Controller Receiver Interrupt USART Controller Interrupt Transmitter Modem Signals Control MCK/DIV SLCK Baud Rate Generator User Interface Table 34-1.
  • Page 731 SAM4S Series [Preliminary] 34.4 Application Block Diagram Figure 34-2. Application Block Diagram IrLAP Field Bus Modem Serial IrDA Driver Driver Driver Driver Driver Driver USART RS232 RS485 Smart IrDA RS232 Drivers Drivers Card Transceivers Drivers Transceiver Slot Modem Differential Serial Port PSTN 34.5...
  • Page 732 34.6 Product Dependencies 34.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The program- mer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller.
  • Page 733 SAM4S Series [Preliminary] 34.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 34-4.
  • Page 734 34.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: •...
  • Page 735 SAM4S Series [Preliminary] This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi- ble clock and that OVER is programmed to 1. Baud Rate Calculation Example Table 34-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies.
  • Page 736 This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate...
  • Page 737 SAM4S Series [Preliminary] 34.7.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: × ----- - where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor •...
  • Page 738 Figure 34-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 34-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 34.7.2 Receiver and Transmitter Control After reset, the receiver is disabled.
  • Page 739 SAM4S Series [Preliminary] The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is sup- ported in asynchronous mode only. Figure 34-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock Start Parity Stop...
  • Page 740 Figure 34-8. NRZ to Manchester Encoding encoded data Manchester encoded data The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times.
  • Page 741 SAM4S Series [Preliminary] character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times.
  • Page 742 Figure 34-11. Bit Resynchronization Oversampling 16x Clock Sampling point Expected edge Sync Synchro. Synchro. Tolerance Jump Error Jump Synchro. Error 34.7.3.3 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over- samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR).
  • Page 743 SAM4S Series [Preliminary] Figure 34-12. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) Sampling 9 10 11 12 13 14 15 16 Start Sampling Detection Sampling Start Rejection Figure 34-13. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock Start samples...
  • Page 744 In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set to one (Rx line is at level 1 if undriven). Figure 34-14.
  • Page 745 SAM4S Series [Preliminary] Figure 34-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time Manchester encoded data Entering USART character area sampling points Preamble subpacket Manchester and Start Frame Delimiter Coding Error were successfully detected decoded When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported.
  • Page 746 Figure 34-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Serial Emitter Configuration RF filter Interface Demod control Manchester USART Fdown frequency Carrier bi-dir decoder Receiver line ASK/FSK downstream transmitter Manchester USART Downstream encoder Emitter Receiver RF filter control The USART module is configured as a Manchester encoder/decoder.
  • Page 747 SAM4S Series [Preliminary] Figure 34-19. FSK Modulator Output NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 34.7.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock.
  • Page 748 Figure 34-21. Receiver Status Baud Rate Clock Start Parity Stop Start Parity Stop RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 34.7.3.8 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode”...
  • Page 749 SAM4S Series [Preliminary] When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1. Figure 34-22 illustrates the parity bit status setting and clearing.
  • Page 750 US_THR. TXEMPTY remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. Figure 34-23. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock Start Parity Stop Start Parity Stop Write US_THR...
  • Page 751 SAM4S Series [Preliminary] • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received.
  • Page 752 Table 34-11. Maximum Time-out Period (Continued) Baud Rate Bit Time Time-out 56000 1 170 57600 1 138 200000 34.7.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
  • Page 753 SAM4S Series [Preliminary] The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result.
  • Page 754 Figure 34-27. Connection with a Remote Device for Hardware Handshaking USART Remote Device Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below.
  • Page 755 SAM4S Series [Preliminary] 34.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.
  • Page 756 the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR).
  • Page 757 SAM4S Series [Preliminary] The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit to 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR).
  • Page 758 34.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 34-12.
  • Page 759 SAM4S Series [Preliminary] Table 34-13. IrDA Baud Rate Error (Continued) Peripheral Clock Baud Rate Baud Rate Error Pulse Time 32 768 000 38 400 0.63% 4.88 40 000 000 38 400 0.16% 4.88 3 686 400 19 200 0.00% 9.77 20 000 000 19 200 0.16%...
  • Page 760 34.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating.
  • Page 761 SAM4S Series [Preliminary] 34.7.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Car- rier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.
  • Page 762 34.7.8 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides com- munication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
  • Page 763 SAM4S Series [Preliminary] 34.7.8.2 Baud Rate In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See “Baud Rate in Synchronous Mode or SPI Mode” on page 736. However, there are some restrictions: In SPI Master Mode: •...
  • Page 764 Figure 34-38. SPI Transfer Format (CPHA=1, 8 bits per transfer) SCK cycle (for reference) (CPOL = 0) (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD SPI Master -> RTS SPI Slave ->...
  • Page 765 SAM4S Series [Preliminary] 34.7.8.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 738. 34.7.8.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI mas- ter mode.
  • Page 766 reception but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 34.7.8.7 Receiver Timeout Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
  • Page 767 SAM4S Series [Preliminary] Figure 34-42. Local Loopback Mode Configuration Receiver Transmitter 34.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 34-43. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
  • Page 768 34.8 Universal Synchronous Asynchronous Receiver Transceiver (USART) User Interface Table 34-16. Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read-write – 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only –...
  • Page 769 SAM4S Series [Preliminary] 34.8.1 USART Control Register Name: US_CR Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only – – – – – – – – – – – – RTSDIS RTSEN DTRDIS DTREN RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA TXDIS TXEN RXDIS...
  • Page 770 • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans- mitted.
  • Page 771 SAM4S Series [Preliminary] • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 11100B–ATARM–31-Jul-12...
  • Page 772 34.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – RSTSTA TXDIS TXEN RXDIS RXEN RSTTX RSTRX...
  • Page 773 SAM4S Series [Preliminary] • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. • FCS: Force SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer).
  • Page 774 34.8.3 USART Mode Register Name: US_MR Address: 0x40024004 (0), 0x40028004 (1) Access: Read-write ONEBIT MODSYNC FILTER – MAX_ITERATION INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF CHMODE NBSTOP SYNC CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register”...
  • Page 775 SAM4S Series [Preliminary] • CHRL: Character Length. Value Name Description 5_BIT Character length is 5 bits 6_BIT Character length is 6 bits 7_BIT Character length is 7 bits 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.
  • Page 776 • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. •...
  • Page 777 SAM4S Series [Preliminary] • MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit.
  • Page 778 34.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0x40024004 (0), 0x40028004 (1) Access: Read-write – – – – – – – – – – – WRDBT – CPOL – – – – – – – CPHA CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register”...
  • Page 779 SAM4S Series [Preliminary] • CHMODE: Channel Mode Value Name Description NORMAL Normal Mode AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. •...
  • Page 780 34.8.5 USART Interrupt Enable Register Name: US_IER Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only – – – – – – – MANE – – – – CTSIC DCDIC DSRIC RIIC – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT PARE FRAME OVRE ENDTX ENDRX...
  • Page 781 SAM4S Series [Preliminary] • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. 11100B–ATARM–31-Jul-12...
  • Page 782 34.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – UNRE TXEMPTY – –...
  • Page 783 SAM4S Series [Preliminary] 34.8.7 USART Interrupt Disable Register Name: US_IDR Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only – – – – – – – MANE – – – – CTSIC DCDIC DSRIC RIIC – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT PARE FRAME...
  • Page 784 • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 785 SAM4S Series [Preliminary] 34.8.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – UNRE TXEMPTY –...
  • Page 786 34.8.9 USART Interrupt Mask Register Name: US_IMR Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only – – – – – – – MANE – – – – CTSIC DCDIC DSRIC RIIC – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT PARE FRAME OVRE ENDTX ENDRX...
  • Page 787 SAM4S Series [Preliminary] • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. 11100B–ATARM–31-Jul-12...
  • Page 788 34.8.10 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – UNRE TXEMPTY – –...
  • Page 789 SAM4S Series [Preliminary] 34.8.11 USART Channel Status Register Name: US_CSR Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only – – – – – – – MANERR CTSIC DCDIC DSRIC RIIC – – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT PARE FRAME OVRE ENDTX ENDRX RXBRK...
  • Page 790 • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA.
  • Page 791 SAM4S Series [Preliminary] • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. •...
  • Page 792 34.8.12 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – UNRE TXEMPTY – –...
  • Page 793 SAM4S Series [Preliminary] 34.8.13 USART Receive Holding Register Name: US_RHR Address: 0x40024018 (0), 0x40028018 (1) Access: Read-only – – – – – – – – – – – – – – – – RXSYNH – – – – – – RXCHR RXCHR •...
  • Page 794 34.8.14 USART Transmit Holding Register Name: US_THR Address: 0x4002401C (0), 0x4002801C (1) Access: Write-only – – – – – – – – – – – – – – – – TXSYNH – – – – – – TXCHR TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
  • Page 795 SAM4S Series [Preliminary] 34.8.15 USART Baud Rate Generator Register Name: US_BRGR Address: 0x40024020 (0), 0x40028020 (1) Access: Read-write – – – – – – – – – – – – – This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register”...
  • Page 796 34.8.16 USART Receiver Time-out Register Name: US_RTOR Address: 0x40024024 (0), 0x40028024 (1) Access: Read-write – – – – – – – – – – – – – – – – This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register”...
  • Page 797 SAM4S Series [Preliminary] 34.8.17 USART Transmitter Timeguard Register Name: US_TTGR Address: 0x40024028 (0), 0x40028028 (1) Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 798 34.8.18 USART FI DI RATIO Register Name: US_FIDI Address: 0x40024040 (0), 0x40028040 (1) Access: Read-write Reset Value: 0x174 – – – – – – – – – – – – – – – – – – – – – FI_DI_RATIO FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register”...
  • Page 799 34.8.19 USART Number of Errors Register Name: US_NER Address: 0x40024044 (0), 0x40028044 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – NB_ERRORS This register is relevant only if USART_MODE=0x4 or 0x6 in “USART Mode Register”...
  • Page 800 34.8.20 USART IrDA FILTER Register Name: US_IF Address: 0x4002404C (0), 0x4002804C (1) Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – IRDA_FILTER This register is relevant only if USART_MODE=0x8 in “USART Mode Register”...
  • Page 801 34.8.21 USART Manchester Configuration Register Name: US_MAN Address: 0x40024050 (0), 0x40028050 (1) Access: Read-write – DRIFT RX_MPOL – – RX_PP – – – – RX_PL – – – TX_MPOL – – TX_PP – – – – TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register”...
  • Page 802 ALL_ZERO The preamble is composed of ‘0’s ZERO_ONE The preamble is composed of ‘01’s ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
  • Page 803 34.8.22 USART Write Protect Mode Register Name: US_WPMR Address: 0x400240E4 (0), 0x400280E4 (1) Access: Read-write Reset: Table 34-16 WPKEY WPKEY WPKEY — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA”...
  • Page 804 34.8.23 USART Write Protect Status Register Name: US_WPSR Address: 0x400240E8 (0), 0x400280E8 (1) Access: Read-only Reset: Table 34-16 — — — — — — — — WPVSRC WPVSRC — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
  • Page 805 SAM4S Series [Preliminary] 35. Timer Counter (TC) 35.1 Description The Timer Counter (TC) includes 3 identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
  • Page 806 • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels • Quadrature decoder – Advanced line filtering –...
  • Page 807: Pc28

    SAM4S Series [Preliminary] Table 35-2. Signal Name Description Block/Channel Signal Name Description XC0, XC1, XC2 External Clock Inputs Capture Mode: Timer Counter Input TIOA Waveform Mode: Timer Counter Output Channel Signal Capture Mode: Timer Counter Input TIOB Waveform Mode: Timer Counter Input/Output Interrupt Signal Output (internal signal) SYNC Synchronization Input Signal (from configuration register)
  • Page 808 Table 35-4. I/O Lines TIOA4 PC26 TIOA5 PC29 TIOB3 PC24 TIOB4 PC27 TIOB5 PC30 35.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 35.5.3 Interrupt The TC has an interrupt line connected to the Interrupt Controller (IC).
  • Page 809 SAM4S Series [Preliminary] The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
  • Page 810 Figure 35-3. Clock Selection TCCLKS CLKI TIMER_CLOCK1 Synchronous Edge Detection TIMER_CLOCK2 TIMER_CLOCK3 Selected TIMER_CLOCK4 Clock TIMER_CLOCK5 BURST 35.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 35-4.
  • Page 811 SAM4S Series [Preliminary] Figure 35-4. Clock Control Selected Trigger Clock CLKSTA CLKEN CLKDIS Stop Disable Event Event Counter Clock 35.6.5 TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation.
  • Page 812 If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 35.6.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs.
  • Page 813 SAM4S Series [Preliminary] 35.6.9 Trigger Conditions TIOA Internal PDC trigger Transfer to System Memory T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK) ETRGEDG=3, LDRA=3, LDRB=0, ABETRG=0 TIOB TIOA Internal PDC trigger Transfer to System Memory T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK) In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trig- ger can be defined.
  • Page 814 Figure 35-5. Capture Mode CPCS LOVRS COVFS LDRBS LDRAS ETRGS TC1_SR TC1_IMR SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 815 SAM4S Series [Preliminary] 35.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same fre- quency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses.
  • Page 816 Figure 35-6. Waveform Mode CPCS CPBS CPAS COVFS ETRGS TC1_SR TC1_IMR SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 817 SAM4S Series [Preliminary] 35.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues.
  • Page 818 Figure 35-8. WAVSEL= 00 with trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF Counter cleared by trigger Time Waveform Examples TIOB TIOA 35.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then auto- matically reset on a RC Compare.
  • Page 819 SAM4S Series [Preliminary] Figure 35-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger Time Waveform Examples TIOB TIOA 35.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on.
  • Page 820 Figure 35-11. WAVSEL = 01 Without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Time Waveform Examples TIOB TIOA Figure 35-12. WAVSEL = 01 With Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger Counter incremented by trigger...
  • Page 821 SAM4S Series [Preliminary] Figure 35-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC Time Waveform Examples TIOB TIOA Figure 35-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC Counter decremented by trigger Counter incremented...
  • Page 822 35.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both).
  • Page 823 SAM4S Series [Preliminary] 35.6.13 Output Controller Timer/Counter TC_EMR0.TRIGSRCA Timer/Counter TIOA0 Channel 0 TIOA0 TC_EMR0.TRIGSRCB TIOB0 TIOB0 TC_EMR1.TRIGSRCA Timer/Counter TIOA1 Channel 1 TIOA1 TC_EMR1.TRIGSRCB TIOB1 TIOB1 TC_EMR2.TRIGSRCA Timer/Counter TIOA2 Channel 2 TIOA2 TC_EMR2TRIGSRCB TIOB2 TIOB2 PWM comparator outputs (internal signals) respectively source of PWMH/L[2:0] The output controller defines the output level changes on TIOA and TIOB following an event.
  • Page 824 When writing 0 in the QDEN field of the TC_BMR register, the quadrature decoder logic is totally transparent. TIOA0 and TIOB0 are to be driven by the 2 dedicated quadrature signals from a rotary sensor mounted on the shaft of the off-chip motor. A third signal from the rotary sensor can be processed through pin TIOB1 and is typically dedi- cated to be driven by an index signal if it is provided by the sensor.
  • Page 825 SAM4S Series [Preliminary] Figure 35-15. Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder (Filter + Edge Timer/Counter TIOA Detect + QD) Channel 0 TIOA0 QDEN PHEdges TIOB TIOB0 TIOA0 Speed/Position TIOB0 QDEN TIOB1 Index TIOB Timer/Counter Channel 1...
  • Page 826 Figure 35-16. Input Stage Input Pre-Processing MAXFILT SWAP FILTER PHedge Filter TIOA0 Direction INVA Edge Detection Filter TIOB0 INVB Filter TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interfer- ence.
  • Page 827 SAM4S Series [Preliminary] Figure 35-17. Filtering Examples MAXFILT=2 particulate contamination PHA,B Filter Out Optical/Magnetic disk strips motor shaft stopped in such a position that rotary sensor cell is aligned with an edge of the disk rotation stop PHB Edge area due to system vibration stop Resulting PHA, PHB electrical waveforms mechanical shock on system...
  • Page 828 35.6.14.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the 2 quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime on TC_QISR register. The polarity of the direction flag status depends on the configuration written in TC_BMR register.
  • Page 829 SAM4S Series [Preliminary] A quadrature error is also reported by the quadrature decoder logic. Rather than reporting an error only when 2 edges occur at the same time on PHA and PHB, which is unlikely to occur in real life, there is a report if the time difference between 2 edges on PHA, PHB is lower than a predefined value.
  • Page 830 In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0 register. Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word. The timer/counter channel 0 is cleared for each increment of IDX count value. Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1.
  • Page 831 SAM4S Series [Preliminary] Figure 35-20. 2-bit Gray Up/Down Counter. WAVEx = GCENx =1 TIOAx TC_RCx TIOBx DOWNx 35.6.16 Write Protection System In order to bring security to the Timer Counter, a write protection system has been implemented. The write protection mode prevent the write of TC_BMR, TC_FMR, TC_CMRx, TC_SMMRx, TC_RAx, TC_RBx, TC_RCx registers.
  • Page 832 35.7 Timer Counter (TC) User Interface Table 35-5. Register Mapping Offset Register Name Access Reset 0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only – 0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read-write 0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR...
  • Page 833 SAM4S Series [Preliminary] 35.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1], 0x40014080 (1)[2] Access: Write-only – – – – – – – – – – – – – – –...
  • Page 834 35.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..2] (WAVE = 0) Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1], 0x40014084 (1)[2] Access: Read-write – – – – – – – – – – – – LDRB LDRA WAVE...
  • Page 835 SAM4S Series [Preliminary] • LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs.
  • Page 836 35.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVE = 1) Access: Read-write BSWTRG BEEVT BCPC BCPB ASWTRG AEEVT ACPC ACPA WAVE WAVSEL ENETRG EEVT EEVTEDG CPCDIS CPCSTOP BURST CLKI TCCLKS This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register”...
  • Page 837 SAM4S Series [Preliminary] • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description NONE None...
  • Page 838 • ACPA: RA Compare Effect on TIOA Value Name Description NONE None CLEAR Clear TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description NONE None CLEAR Clear TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description NONE...
  • Page 839 SAM4S Series [Preliminary] • BCPC: RC Compare Effect on TIOB Value Name Description NONE None CLEAR Clear TOGGLE Toggle • BEEVT: External Event Effect on TIOB Value Name Description NONE None CLEAR Clear TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB Value Name Description...
  • Page 840 35.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..2] Address: 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1], 0x40014088 (1)[2] Access: Read-write – – – – – – – – – – – – – – – – –...
  • Page 841 SAM4S Series [Preliminary] 35.7.5 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1], 0x40014090 (1)[2] Access: Read-only • CV: Counter Value CV contains the counter value in real time. 11100B–ATARM–31-Jul-12...
  • Page 842 35.7.6 TC Register A Name: TC_RAx [x=0..2] Address: 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1], 0x40014094 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register”...
  • Page 843 SAM4S Series [Preliminary] 35.7.8 TC Register C Name: TC_RCx [x=0..2] Address: 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1], 0x4001409C (1)[2] Access: Read-write This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 858 •...
  • Page 844 35.7.9 TC Status Register Name: TC_SRx [x=0..2] Address: 0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100A0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1], 0x400140A0 (1)[2] Access: Read-only – – – – – – – – – – – – – MTIOB MTIOA CLKSTA – – –...
  • Page 845 SAM4S Series [Preliminary] • ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0 = Clock is disabled.
  • Page 846 35.7.10 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1], 0x400140A4 (1)[2] Access: Write-only – – – – – – – – – – – – – – – – – –...
  • Page 847 SAM4S Series [Preliminary] 35.7.11 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1], 0x400140A8 (1)[2] Access: Write-only – – – – – – – – – – – – – – –...
  • Page 848 • ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 849 SAM4S Series [Preliminary] 35.7.12 TC Interrupt Mask Register Name: TC_IMRx [x=0..2] Address: 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1], 0x400140AC (1)[2] Access: Read-only – – – – – – – – – – – – – – –...
  • Page 850 35.7.13 TC Block Control Register Name: TC_BCR Address: 0x400100C0 (0), 0x400140C0 (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 851 SAM4S Series [Preliminary] 35.7.14 TC Block Mode Register Name: TC_BMR Address: 0x400100C4 (0), 0x400140C4 (1) Access: Read-write – – – – – – MAXFILT MAXFILT FILTER – IDXPHB SWAP INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN – – TC2XC2S TC1XC1S TC0XC0S This register can only be written if the WPEN bit is cleared in...
  • Page 852 One of the POSEN or SPEEDEN bits must be also enabled. • POSEN: POSition ENabled 0 = Disable position. 1 = Enables the position measure on channel 0 and 1. • SPEEDEN: SPEED ENabled 0 = Disabled. 1 = Enables the speed measure on channel 0, the time base being provided by channel 2. •...
  • Page 853 SAM4S Series [Preliminary] 35.7.15 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0x400100C8 (0), 0x400140C8 (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 854 35.7.16 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0x400100CC (0), 0x400140CC (1) Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 855 SAM4S Series [Preliminary] 35.7.17 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0x400100D0 (0), 0x400140D0 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 856 35.7.18 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0x400100D4 (0), 0x400140D4 (1) Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 857 SAM4S Series [Preliminary] 35.7.19 TC Fault Mode Register Name: TC_FMR Address: 0x400100D8 (0), 0x400140D8 (1) Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 858 35.7.20 TC Write Protect Mode Register Name: TC_WPMR Address: 0x400100E4 (0), 0x400140E4 (1) Access: Read-write WPKEY WPKEY WPKEY – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x54494D (“TIM”...
  • Page 859 SAM4S Series [Preliminary] 36. High Speed Multimedia Card Interface (HSMCI) 36.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.
  • Page 860 36.3 Block Diagram Figure 36-1. Block Diagram APB Bridge MCCK MCCDA MCDA0 HSMCI Interface MCDA1 MCDA2 MCDA3 Interrupt Control HSMCI Interrupt SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 861 SAM4S Series [Preliminary] 36.4 Application Block Diagram Figure 36-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 2 3 4 5 6 2 3 4 5 6 9 1011 1213 8 SDCard 36.5 Pin Name List Table 36-1.
  • Page 862: Pa28

    36.6 Product Dependencies 36.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral func- tions to HSMCI pins. Table 36-2.
  • Page 863 SAM4S Series [Preliminary] The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 36-4. Bus Topology HSMCI Pin Name Number Name Type Description (Slot z) DAT[3] I/O/PP Data MCDz3...
  • Page 864 Figure 36-5. SD Memory Card Bus Topology 2 3 4 5 6 SD CARD The SD Memory Card bus includes the signals listed in Table 36-5. Table 36-5. SD Memory Card Bus Signals HSMCI Pin Name Number Name Type Description (Slot z) CD/DAT[3] I/O/PP...
  • Page 865 SAM4S Series [Preliminary] 36.8 High Speed MultiMediaCard Operations After a power-on reset, the cards are initialized by a special message-based High Speed Multi- MediaCard bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command).
  • Page 866 The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI command register. The HSMCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command Cycles Content ****** Content...
  • Page 867 SAM4S Series [Preliminary] Figure 36-7. Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command CMDRDY ready status flag Check error bits in the Status error flags? status register RETURN ERROR Read response if required Does the command involve...
  • Page 868 36.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in HSMCI_MR, then all reads and writes use the PDC facilities.
  • Page 869 SAM4S Series [Preliminary] Figure 36-8. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command to select the card Send SET_BLOCKLEN command Read with PDC Reset the PDCMODE bit Set the PDCMODE bit HSMCI_MR &= ~PDCMODE HSMCI_MR |= PDCMODE Set the block length (in bytes) Set the block length (in bytes) HSMCI_MR |= (BlockLenght <<16) HSMCI_MR |= (BlockLength <<...
  • Page 870 36.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer.
  • Page 871 SAM4S Series [Preliminary] Figure 36-9. Write Functional Flow Diagram Send SELECT/DESELECT_CARD command to select the card Send SET_BLOCKLEN command Write using PDC Reset the PDCMODE bit Set the PDCMODE bit HSMCI_MR &= ~PDCMODE HSMCI_MR |= PDCMODE Set the block length Set the block length HSMCI_MR |= (BlockLenght <<16) HSMCI_MR |= (BlockLength <<...
  • Page 872 The following flowchart (Figure 36-10) shows how to manage a multiple write block transfer with the PDC. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR). Figure 36-10.
  • Page 873 SAM4S Series [Preliminary] 36.9 SD/SDIO Card Operation The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
  • Page 874 36.10 CE-ATA Operation CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space. CE-ATA utilizes five MMC commands: • GO_IDLE_STATE (CMD0): used for hard reset. • STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted.
  • Page 875 SAM4S Series [Preliminary] • Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response. • Issue a software reset to the CE-ATA device using FAST_IO (CMD39). If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com- mands. However, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device.
  • Page 876 36.12 HSMCI Transfer Done Timings 36.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 36.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 36-11. Figure 36-11. XFRDONE During a Read Access CMD line HSMCI read CMD Card response...
  • Page 877 SAM4S Series [Preliminary] 36.13 Write Protection Registers To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register” (HSMCI_WPMR).
  • Page 878 36.14 High Speed Multimedia Card Interface (HSMCI) User Interface Table 36-8. Register Mapping Offset Register Name Access Reset 0x00 Control Register HSMCI_CR Write – 0x04 Mode Register HSMCI_MR Read-write 0x08 Data Timeout Register HSMCI_DTOR Read-write 0x0C SD/SDIO Card Register HSMCI_SDCR Read-write 0x10 Argument Register...
  • Page 879 SAM4S Series [Preliminary] 36.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0x40000000 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – SWRST – – –...
  • Page 880 36.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0x40000004 Access: Read-write – – – – – – – – – – – – – – – – PDCMODE PADV FBYTE WRPROOF RDPROOF PWSDIV CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register”...
  • Page 881 SAM4S Series [Preliminary] • PADV: Padding Value 0 = 0x00 value is used when padding data in write transfer. 1 = 0xFF value is used when padding data in write transfer. PADV may be only in manual transfer. • PDCMODE: PDC-oriented Mode 0 = Disables PDC transfer 1 = Enables PDC transfer.
  • Page 882 36.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0x40000008 Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – – DTOMUL DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register”...
  • Page 883 SAM4S Series [Preliminary] 36.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0x4000000C Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – SDCBUS – – –...
  • Page 884 36.14.5 HSMCI Argument Register Name: HSMCI_ARGR Address: 0x40000010 Access: Read-write • ARG: Command Argument SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 885 SAM4S Series [Preliminary] 36.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0x40000014 Access: Write-only – – – – BOOT_ACK ATACS IOSPCMD – – TRTYP TRDIR TRCMD – – – MAXLAT OPDCMD SPCMD RSPTYP CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writ- able by an interrupt response (field SPCMD).
  • Page 886 Value Name Description Interrupt response: IT_RESP Corresponds to the Interrupt Mode (CMD40). Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. End Boot Operation. This command allows the host processor to terminate the boot operation mode. •...
  • Page 887 SAM4S Series [Preliminary] • ATACS: ATA with Command Completion Signal 0 (NORMAL) = Normal operation mode. 1 (COMPLETION) = This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). • BOOT_ACK: Boot Operation Acknowledge. The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued.
  • Page 888 36.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0x40000018 Access: Read-write BLKLEN BLKLEN BCNT BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Com- mand Register (HSMCI_CMDR): Value Name...
  • Page 889 SAM4S Series [Preliminary] 36.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0x4000001C Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – – CSTOMUL CSTOCYC This register can only be written if the WPEN bit is cleared in...
  • Page 890 36.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0x40000020 Access: Read-only • RSP: Response Note: The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. SAM4S Series [Preliminary] 11100B–ATARM–31-Jul-12...
  • Page 891 SAM4S Series [Preliminary] 36.14.10 HSMCI Receive Data Register Name: HSMCI_RDR Address: 0x40000030 Access: Read-only DATA DATA DATA DATA • DATA: Data to Read 36.14.11 HSMCI Transmit Data Register Name: HSMCI_TDR Address: 0x40000034 Access: Write-only DATA DATA DATA DATA • DATA: Data to Write 11100B–ATARM–31-Jul-12...
  • Page 892 36.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0x40000040 Access: Read-only UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – – CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY •...
  • Page 893 SAM4S Series [Preliminary] 0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card.
  • Page 894 • RINDE: Response Index Error 0 = No error. 1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the HSMCI_CMDR. • RDIRE: Response Direction Error 0 = No error. 1 = The direction bit from card to host in the response has not been detected.
  • Page 895 SAM4S Series [Preliminary] • ACKRCV: Boot Operation Acknowledge Received 0 = No Boot acknowledge received since the last read of the status register. 1 = A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register. • ACKRCVE: Boot Operation Acknowledge Error 0 = No error 1 = Corrupted Boot Acknowledge signal received.
  • Page 896 36.14.13 HSMCI Interrupt Enable Register Name: HSMCI_IER Address: 0x40000044 Access: Write-only UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – – CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY...
  • Page 897 SAM4S Series [Preliminary] • DCRCE: Data CRC Error Interrupt Enable • DTOE: Data Time-out Error Interrupt Enable • CSTOE: Completion Signal Timeout Error Interrupt Enable • FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable •...
  • Page 898 36.14.14 HSMCI Interrupt Disable Register Name: HSMCI_IDR Address: 0x40000048 Access: Write-only UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – – CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY...
  • Page 899 SAM4S Series [Preliminary] • DTOE: Data Time-out Error Interrupt Disable • CSTOE: Completion Signal Time out Error Interrupt Disable • FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable •...
  • Page 900 36.14.15 HSMCI Interrupt Mask Register Name: HSMCI_IMR Address: 0x4000004C Access: Read-only UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – – CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY...
  • Page 901 SAM4S Series [Preliminary] • DTOE: Data Time-out Error Interrupt Mask • CSTOE: Completion Signal Time-out Error Interrupt Mask • FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask •...
  • Page 902 36.14.16 HSMCI Configuration Register Name: HSMCI_CFG Address: 0x40000054 Access: Read-write – – – – – – – – – – – – – – – – – LSYNC – – – HSMODE – – – FERRCTRL – – – FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register”...
  • Page 903 SAM4S Series [Preliminary] 36.14.17 HSMCI Write Protect Mode Register Name: HSMCI_WPMR Address: 0x400000E4 Access: Read-write WP_KEY (0x4D => “M”) WP_KEY (0x43 => C”) WP_KEY (0x49 => “I”) WP_EN • WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII). 1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’...
  • Page 904 36.14.18 HSMCI Write Protect Status Register Name: HSMCI_WPSR Address: 0x400000E8 Access: Read-only – – – – – – – – WP_VSRC WP_VSRC – – – – WP_VS • WP_VS: Write Protection Violation Status Value Name Description No Write Protection Violation occurred since the last read of this NONE register (WP_SR) Write Protection detected unauthorized attempt to write a control...
  • Page 905 SAM4S Series [Preliminary] 37. Pulse Width Modulation Controller (PWM) 37.1 Description The Pulse Width Modulation Controller (PWM) macrocell controls 4 channels independently. Each channel controls two complementary square output waveforms. Characteristics of the out- put waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface.
  • Page 906 – Independent Clock Selection – Independent Period and Duty Cycle, with Double Buffering • Synchronous Channel mode – Synchronous Channels share the same counter – Mode to update the synchronous channels registers after a programmable number of periods • Connection to one PDC channel –...
  • Page 907: Pa29

    SAM4S Series [Preliminary] 37.4 I/O Lines Description Each channel outputs two complementary external I/O lines. Table 37-1. I/O Line Description Name Description Type PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output PWMFIx PWM Fault Input x...
  • Page 908: Pa30

    Table 37-2. I/O Lines PWMH3 PC21 PWML0 PA19 PWML0 PWML0 PWML0 PC13 PWML1 PA20 PWML1 PB12 PWML1 PWML1 PC15 PWML2 PA16 PWML2 PA30 PWML2 PB13 PWML2 PWML3 PA15 PWML3 PWML3 PC22 37.5.2 Power Management The PWM is not continuously clocked. The programmer must first enable the clock in the Power Management Controller (PMC) before using the .
  • Page 909 SAM4S Series [Preliminary] Table 37-4. Fault Inputs Fault Inputs External PWM Fault Input Number Polarity Level Fault Input ID PWMFI0 User Defined Main OSC – – Analog Comparator – Timer0 Timer1 – Note: 1. FPOL bit in PWMC_FMR. 37.6 Functional Description macrocell is primarily composed of a clock generator module and 4 channels.
  • Page 910 37.6.1 PWM Clock Generator Figure 37-2. Functional View of the Clock Generator Block Diagram modulo n counter MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A clkA PREA DIVA PWM_MR Divider B clkB PREB DIVB PWM_MR The PWM master clock (MCK) is divided in the clock generator module to provide different clocks available for all channels.
  • Page 911 SAM4S Series [Preliminary] At reset, all clocks provided by the modulo n counter are turned off except clock ”MCK”. This sit- uation is also true when the PWM master clock is turned off through the Power Management Controller. CAUTION: • Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC).
  • Page 912 • A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external power control switches safely. • An output override block that can force the two complementary outputs to a programmed value (OOOHx/OOOLx). • An asynchronous fault protection mechanism that has the highest priority to override the two complementary outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to 0, 1).
  • Page 913 SAM4S Series [Preliminary] ⁄ × period 1 – fchannel_x_clock CDTY duty cycle ----------------------------------------------------------------------------------------------------------- - period If the waveform is center aligned, then: ⁄ ⁄ × fchannel_x_clock period – CDTY duty cycle ----------------------------------------------------------------------------------------------------------------------------- - ⁄ period • the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register.
  • Page 914 occurs at the end of the counter period. If CES is set to 1, the interrupt occurs at the end of the counter period and at half of the counter period. Figure 37-5 “Waveform Properties” illustrates the counter interrupts in function of the configuration.
  • Page 915 SAM4S Series [Preliminary] 37.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor It is possible to configure a couple of channels to provide a 2-bit gray count waveform on 2 out- puts. Dead-Time Generator and other downstream logic can be configured on these channels. Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration registers.
  • Page 916 Figure 37-7. Complementary Output Waveforms output waveform OCx CPOLx = 0 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 DTHx DTLx output waveform OCx CPOLx = 1 output waveform DTOHx DTHIx = 0...
  • Page 917 SAM4S Series [Preliminary] By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM outputs is done synchronously to the channel counter, at the beginning of the next PWM period. By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the channel counter, as soon as the register is written.
  • Page 918 current level of the fault inputs by means of the field FIV, and can know which fault is currently active thanks to the FS field. Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into account in the channel x, the fault y must be enabled by the bit FPEx[y] in the “PWM Fault Protection Enable Registers”...
  • Page 919 SAM4S Series [Preliminary] 37.6.2.7 Synchronous Channels Some channels can be linked together as synchronous channels. They have the same source clock, the same period, the same alignment and are started together. In this way, their counters are synchronized together. The synchronous channels are defined by the SYNCx bits in the “PWM Sync Channels Mode Register”...
  • Page 920 Update Period Register” (PWM_SCUP) (see “Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 921). • Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous channels are written by the Peripheral DMA Controller (PDC) (see “Method 3: Automatic write of duty-cycle values and automatic trigger of the update”...
  • Page 921 SAM4S Series [Preliminary] Sequence for Method 1: 1. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to 0 in the PWM_SCM register 2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register. 3.
  • Page 922 The status of the duty-cycle value write is reported in the “PWM Interrupt Status Register 2” (PWM_ISR2) by the following flags: • WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle values and a new update period value. It is reset to 0 when the PWM_ISR2 register is read. Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by these flags.
  • Page 923 SAM4S Series [Preliminary] Method 3: Automatic write of duty-cycle values and automatic trigger of the update In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA Controller (PDC). The update of the period value, the dead-time values and the update period value must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_DTUPDx and PWM_SCUPUPD).
  • Page 924 Sequence for Method 3: 1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the PWM_SCM register. 2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register. 3. Define the update period by the field UPR in the PWM_SCUP register. 4.
  • Page 925 SAM4S Series [Preliminary] Figure 37-13. Method 3 (UPDM=2 and PTRM=1 and PTRCS=0) CCNT0 0x60 0x80 0xB0 0x20 0x40 0xA0 CDTYUPD UPRUPD UPRCNT 0x60 0x80 0x40 0xA0 0x20 CDTY CMP0 match transfer request WRDY 37.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 37.6.2.7 “Synchronous...
  • Page 926 The comparison x matches when it is enabled by the bit CEN in the “PWM Comparison x Mode Register” (PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value defined by the field CV in “PWM Comparison x Value Register”...
  • Page 927 SAM4S Series [Preliminary] Figure 37-15. Comparison Waveform CCNT0 CVUPD CVMVUPD CTRUPD CPRUPD CUPRUPD CUPR CUPRCNT CPRCNT Comparison Update CMPU Comparison Match CMPM 37.6.4 PWM Event Lines The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in particular for ADC (Analog-to-Digital Converter)).
  • Page 928 Figure 37-16. Event Line Block Diagram CMPM0 (PWM_ISR2) CSEL0 (PWM_ELMRx) CMPM1 (PWM_ISR2) CSEL1 (PWM_ELMRx) CMPM2 (PWM_ISR2) CSEL2 (PWM_ELMRx) Event Line x PULSE GENERATOR CMPM7 (PWM_ISR2) CSEL7 (PWM_ELMRx) 37.6.5 PWM Controller Operations 37.6.5.1 Initialization Before enabling the channels, they must have been configured by the software application: •...
  • Page 929 SAM4S Series [Preliminary] • Configuration of the event lines (PWM_ELMRx). • Configuration of the fault inputs polarity (FPOL in PWM_FMR) • Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE1) • Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing WRDYE, ENDTXE, TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register) •...
  • Page 930 Figure 37-17. Synchronized Period, Duty-Cycle and Dead-Times Update User's Writing User's Writing User's Writing PWM_DTUPDx Value PWM_CPRDUPDx Value PWM_CDTYUPDx Value PWM_CPRDx PWM_CDTYx PWM_DTx - If Asynchronous Channel -> End of PWM period - If Synchronous Channel -> End of PWM period and UPDULOCK = 1 - If Asynchronous Channel ->...
  • Page 931 SAM4S Series [Preliminary] Figure 37-18. Synchronized Update of Update Period Value of Synchronous Channels User's Writing PWM_SCUPUPD Value PWM_SCUP End of PWM period and end of Update Period of Synchronous Channels 37.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see Section 37.6.3 “PWM Comparison...
  • Page 932 Figure 37-19. Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPVUPDx Value PWM_CMPMUPDx Value Comparison Value Comparison configuration for comparison x for comparison x PWM_CMPVx PWM_CMPMx End of channel0 PWM period and end of Comparison Update Period and and PWM_CMPMx written End of channel0 PWM period and end of Comparison Update Period...
  • Page 933 SAM4S Series [Preliminary] • Register group 2: – “PWM Sync Channels Mode Register” on page 942 – “PWM Channel Mode Register” on page 970 – “PWM Stepper Motor Mode Register” on page 962 – • Register group 3: – “PWM Channel Period Register” on page 974 –...
  • Page 934 37.7 Pulse Width Modulation Controller (PWM) Controller User Interface Table 37-6. Register Mapping Offset Register Name Access Reset 0x00 PWM Clock Register PWM_CLK Read-write 0x04 PWM Enable Register PWM_ENA Write-only – 0x08 PWM Disable Register PWM_DIS Write-only – 0x0C PWM Status Register PWM_SR Read-only 0x10...
  • Page 935 SAM4S Series [Preliminary] Table 37-6. Register Mapping (Continued) Offset Register Name Access Reset 0xB4-0xBC Reserved – – – 0xC0-E0 Reserved – – – 0xE4 PWM Write Protect Control Register PWM_WPCR Write-only – 0xE8 PWM Write Protect Status Register PWM_WPSR Read-only 0xEC - 0xFC Reserved –...
  • Page 936 Table 37-6. Register Mapping (Continued) Offset Register Name Access Reset 0x1A4 PWM Comparison 7 Value Update Register PWM_CMPVUPD7 Write-only – 0x1A8 PWM Comparison 7 Mode Register PWM_CMPM7 Read-write 0x1AC PWM Comparison 7 Mode Update Register PWM_CMPMUPD7 Write-only – 0x1B0 - 0x1FC Reserved –...
  • Page 937 SAM4S Series [Preliminary] 37.7.1 PWM Clock Register Name: PWM_CLK Address: 0x40020000 Access: Read-write – – – – PREB DIVB – – – – PREA DIVA This register can only be written if the bits WPSWS0 and WPHWS0 are cleared in “PWM Write Protect Status Register”...
  • Page 938 37.7.2 PWM Enable Register Name: PWM_ENA Address: 0x40020004 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – – – – – – CHID3 CHID2 CHID1 CHID0 •...
  • Page 939 SAM4S Series [Preliminary] 37.7.4 PWM Status Register Name: PWM_SR Address: 0x4002000C Access: Read-only – – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 940 37.7.6 PWM Interrupt Disable Register 1 Name: PWM_IDR1 Address: 0x40020014 Access: Write-only – – – – – – – – – – – – FCHID3 FCHID2 FCHID1 FCHID0 – – – – – – – – – – – – CHID3 CHID2 CHID1...
  • Page 941 SAM4S Series [Preliminary] 37.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Address: 0x4002001C Access: Read-only – – – – – – – – – – – – FCHID3 FCHID2 FCHID1 FCHID0 – – – – – – – – – –...
  • Page 942 37.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Address: 0x40020020 Access: Read-write – – – – – – – – PTRCS PTRM – – UPDM – – – – – – – – – – – – SYNC3 SYNC2 SYNC1 SYNC0 This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register”...
  • Page 943 SAM4S Series [Preliminary] • PTRCS: PDCDMA Transfer Request Comparison Selection Selection of the comparison used to set the flag WRDY and the corresponding transfer request. 37.7.10 PWM Sync Channels Update Control Register Name: PWM_SCUC Address: 0x40020028 Access: Read-write – – –...
  • Page 944 37.7.11 PWM Sync Channels Update Period Register Name: PWM_SCUP Address: 0x4002002C Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – UPRCNT • UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register”...
  • Page 945 SAM4S Series [Preliminary] 37.7.12 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Address: 0x40020030 Access: Write-only – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 946 37.7.13 PWM Interrupt Enable Register 2 Name: PWM_IER2 Address: 0x40020034 Access: Write-only – – – – – – – – CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 – – – – UNRE TXBUFE ENDTX...
  • Page 947 SAM4S Series [Preliminary] 37.7.14 PWM Interrupt Disable Register 2 Name: PWM_IDR2 Address: 0x40020038 Access: Write-only – – – – – – – – CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 – –...
  • Page 948 37.7.15 PWM Interrupt Mask Register 2 Name: PWM_IMR2 Address: 0x4002003C Access: Read-only – – – – – – – – CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 – – – – UNRE TXBUFE ENDTX...
  • Page 949 SAM4S Series [Preliminary] 37.7.16 PWM Interrupt Status Register 2 Name: PWM_ISR2 Address: 0x40020040 Access: Read-only – – – – – – – – CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0 – –...
  • Page 950 37.7.17 PWM Output Override Value Register Name: PWM_OOV Address: 0x40020044 Access: Read-write – – – – – – – – – – – – OOVL3 OOVL2 OOVL1 OOVL0 – – – – – – – – – – – – OOVH3 OOVH2 OOVH1...
  • Page 951 SAM4S Series [Preliminary] 37.7.18 PWM Output Selection Register Name: PWM_OS Address: 0x40020048 Access: Read-write – – – – – – – – – – – – OSL3 OSL2 OSL1 OSL0 – – – – – – – – – – –...
  • Page 952 37.7.19 PWM Output Selection Set Register Name: PWM_OSS Address: 0x4002004C Access: Write-only – – – – – – – – – – – – OSSL3 OSSL2 OSSL1 OSSL0 – – – – – – – – – – – – OSSH3 OSSH2 OSSH1...
  • Page 953 SAM4S Series [Preliminary] 37.7.20 PWM Output Selection Clear Register Name: PWM_OSC Address: 0x40020050 Access: Write-only – – – – – – – – – – – – OSCL3 OSCL2 OSCL1 OSCL0 – – – – – – – – – –...
  • Page 954 37.7.21 PWM Output Selection Set Update Register Name: PWM_OSSUPD Address: 0x40020054 Access: Write-only – – – – – – – – – – – – OSSUPL3 OSSUPL2 OSSUPL1 OSSUPL0 – – – – – – – – – – – –...
  • Page 955 SAM4S Series [Preliminary] 37.7.22 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Address: 0x40020058 Access: Write-only – – – – – – – – – – – – OSCUPL3 OSCUPL2 OSCUPL1 OSCUPL0 – – – – – – – – –...
  • Page 956 37.7.23 PWM Fault Mode Register Name: PWM_FMR Address: 0x4002005C Access: Read-write – FFIL FMOD FPOL This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 965. • FPOL: Fault Polarity (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The fault y becomes active when the fault input y is at 0.
  • Page 957 SAM4S Series [Preliminary] 37.7.24 PWM Fault Status Register Name: PWM_FSR Address: 0x40020060 Access: Read-only – – • FIV: Fault Input Value (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The current sampled value of the fault input y is 0 (after filtering if enabled). 1 = The current sampled value of the fault input y is 1 (after filtering if enabled).
  • Page 958 37.7.25 PWM Fault Clear Register Name: PWM_FCR Address: 0x40020064 Access: Write-only – – – FCLR • FCLR: Fault Clear (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = No effect. 1 = If bit y of FMOD field is set to 1 and if the fault input y is not at the level defined by the bit y of FPOL field, the fault y is cleared and becomes inactive (FMOD and FPOL fields belong to “PWM Fault Mode Register”...
  • Page 959 SAM4S Series [Preliminary] 37.7.26 PWM Fault Protection Value Register Name: PWM_FPV Address: 0x40020068 Access: Read-write – – – – – – – – – – – – FPVL3 FPVL2 FPVL1 FPVL0 – – – – – – – – – –...
  • Page 960 37.7.27 PWM Fault Protection Enable Register Name: PWM_FPE Address: 0x4002006C Access: Read-write FPE3 FPE2 FPE1 FPE0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 965. Only the first 6 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant. •...
  • Page 961 SAM4S Series [Preliminary] 37.7.28 PWM Event Line x Register Name: PWM_ELMRx Address: 0x4002007C Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – CSEL7 CSEL6 CSEL5 CSEL4...
  • Page 962 37.7.29 PWM Stepper Motor Mode Register Name: PWM_SMMR Address: 0x400200B0 Access: Read-write – – – – – – – – – – – – – – DOWN1 DOWN0 – – – – – – – – – – – – –...
  • Page 963 SAM4S Series [Preliminary] 37.7.30 PWM Write Protect Control Register Name: PWM_WPCR Address: 0x400200E4 Access: Write-only WPKEY WPKEY WPKEY WPRG5 WPRG4 WPRG3 WPRG2 WPRG1 WPRG0 WPCMD • WPCMD: Write Protect Command This command is performed only if the WPKEY value is correct. 0 = Disable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
  • Page 964 • Register group 3: – “PWM Channel Period Register” on page 974 – “PWM Channel Period Update Register” on page 975 • Register group 4: – “PWM Channel Dead Time Register” on page 977 – “PWM Channel Dead Time Update Register” on page 978 •...
  • Page 965 SAM4S Series [Preliminary] 37.7.31 PWM Write Protect Status Register Name: PWM_WPSR Address: 0x400200E8 Access: Read-only WPVSRC WPVSRC – – WPHWS5 WPHWS4 WPHWS3 WPHWS2 WPHWS1 WPHWS0 WPVS – WPSWS5 WPSWS4 WPSWS3 WPSWS2 WPSWS1 WPSWS0 • WPSWSx: Write Protect SW Status 0 = The Write Protect SW x of the register group x is disabled. 1 = The Write Protect SW x of the register group x is enabled.
  • Page 966 37.7.32 PWM Comparison x Value Register Name: PWM_CMPVx Address: 0x40020130 [0], 0x40020140 [1], 0x40020150 [2], 0x40020160 [3], 0x40020170 [4], 0x40020180 [5], 0x40020190 [6], 0x400201A0 [7] Access: Read-write – – – – – – – Only the first 16 bits (channel counter size) of field CV are significant. •...
  • Page 967 SAM4S Series [Preliminary] 37.7.33 PWM Comparison x Value Update Register Name: PWM_CMPVUPDx Address: 0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5], 0x40020194 [6], 0x400201A4 [7] Access: Write-only – – – – – – – CVMUPD CVUPD CVUPD CVUPD This register acts as a double buffer for the CV and CVM values.
  • Page 968 37.7.34 PWM Comparison x Mode Register Name: PWM_CMPMx Address: 0x40020138 [0], 0x40020148 [1], 0x40020158 [2], 0x40020168 [3], 0x40020178 [4], 0x40020188 [5], 0x40020198 [6], 0x400201A8 [7] Access: Read-write – – – – – – – – CUPRCNT CUPR CPRCNT – – –...
  • Page 969 SAM4S Series [Preliminary] 37.7.35 PWM Comparison x Mode Update Register Name: PWM_CMPMUPDx Address: 0x4002013C [0], 0x4002014C [1], 0x4002015C [2], 0x4002016C [3], 0x4002017C [4], 0x4002018C [5], 0x4002019C [6], 0x400201AC [7] Access: Write-only – – – – – – – – – –...
  • Page 970 37.7.36 PWM Channel Mode Register Name: PWM_CMRx [x=0..3] Address: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3] Access: Read-write – – – – – – – – – – – – – DTLI DTHI – – – – – CPOL CALG –...
  • Page 971 SAM4S Series [Preliminary] • CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in the “PWM Interrupt Status Register 1” on page 941). CALG = 0 (Left Alignment): 0/1 = The channel counter event occurs at the end of the PWM period.
  • Page 972 37.7.37 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..3] Address: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3] Access: Read-write – – – – – – – – CDTY CDTY CDTY Only the first 16 bits (channel counter size) are significant. •...
  • Page 973 SAM4S Series [Preliminary] 37.7.38 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..3] Address: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3] Access: Write-only. – – – – – – – – CDTYUPD CDTYUPD CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the wave- form duty-cycle.
  • Page 974 37.7.39 PWM Channel Period Register Name: PWM_CPRDx [x=0..3] Address: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3] Access: Read-write – – – – – – – – CPRD CPRD CPRD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register”...
  • Page 975 SAM4S Series [Preliminary] 37.7.40 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..3] Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3] Access: Write-only – – – – – – – – CPRDUPD CPRDUPD CPRDUPD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register”...
  • Page 976 37.7.41 PWM Channel Counter Register Name: PWM_CCNTx [x=0..3] Address: 0x40020214 [0], 0x40020234 [1], 0x40020254 [2], 0x40020274 [3] Access: Read-only – – – – – – – – Only the first 16 bits (channel counter size) are significant. • CNT: Channel Counter Register Channel counter value.
  • Page 977 SAM4S Series [Preliminary] 37.7.42 PWM Channel Dead Time Register Name: PWM_DTx [x=0..3] Address: 0x40020218 [0], 0x40020238 [1], 0x40020258 [2], 0x40020278 [3] Access: Read-write This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 965.
  • Page 978 37.7.43 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..3] Address: 0x4002021C [0], 0x4002023C [1], 0x4002025C [2], 0x4002027C [3] Access: Write-only DTLUPD DTLUPD DTHUPD DTHUPD This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register”...
  • Page 979 SAM4S Series [Preliminary] 38. USB Device Port (UDP) 38.1 Description The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload.
  • Page 980 38.3 Block Diagram Figure 38-1. Block Diagram Atmel Bridge USB Device txoen eopn Serial Dual Interface UDPCK Embedded Port Engine rxdm Transceiver FIFO 12 MHz rxdp udp_int Suspend/Resume Logic Master Clock Recovered 12 MHz Domain Domain Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers.
  • Page 981 SAM4S Series [Preliminary] 38.4 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Prop- erties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host.
  • Page 982 38.5 Typical Connection Figure 38-2. Board Schematic to Interface Device Peripheral 27 K 5V Bus Monitoring 47 K Type B Connector 38.5.1 USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows: •...
  • Page 983 SAM4S Series [Preliminary] Figure 38-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.0 Software Client 1 Software Client 2 Data Flow: Control Transfer USB Device 2.0 Data Flow: Isochronous In Transfer Block 1 Data Flow: Isochronous Out Transfer Data Flow: Control Transfer USB Device 2.0 Data Flow: Bulk In Transfer...
  • Page 984 38.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 38-5. USB Transfer Events • Setup transaction > Data IN transactions > Status OUT transaction (1) (3) • Setup transaction > Data OUT transactions > Status Control Transfers IN transaction •...
  • Page 985 SAM4S Series [Preliminary] Figure 38-5. Control Read and Write Sequences Setup Stage Data Stage Status Stage Setup TX Data OUT TX Data OUT TX Status IN TX Control Read Setup Stage Data Stage Status Stage Setup TX Data IN TX Data IN TX Control Write Status OUT TX...
  • Page 986 Figure 38-6. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received Setup Data OUT Data OUT Data Setup Data OUT Data OUT Bus Packets RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral...
  • Page 987 SAM4S Series [Preliminary] Figure 38-7. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus Data IN Data IN Data IN USB Bus Packets Data IN 1 Data IN 2 TXPKTRDY Flag (UDP_CSRx) Set by the firmware...
  • Page 988 When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register.
  • Page 989 SAM4S Series [Preliminary] 38.6.2.3 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and con- duct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1.
  • Page 990 banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 38-11. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller USB Device USB Bus Read Write Data IN Packet Bank 0 Write and Read at the Same Time Endpoint 1...
  • Page 991 SAM4S Series [Preliminary] 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0.
  • Page 992 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set.
  • Page 993 SAM4S Series [Preliminary] 38.6.2.5 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 38-1 ”USB Endpoint Description”.
  • Page 994 38.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Speci- fication, Rev 2.0. Figure 38-15. USB Device State Diagram Attached Hub Reset Configured Deconfigured Bus Inactive Powered Suspended Bus Activity Power Interruption Reset...
  • Page 995 SAM4S Series [Preliminary] 38.6.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ...
  • Page 996 register. This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an exam- ple, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode.
  • Page 997 SAM4S Series [Preliminary] 38.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 38-6. Register Mapping Offset Register Name...
  • Page 998 38.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0x40034000 Access: Read-only – – – – – – FRM_OK FRM_ERR – – – – – FRM_NUM FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet).
  • Page 999 SAM4S Series [Preliminary] 38.7.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0x40034004 Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – – – –...
  • Page 1000 38.7.3 UDP Function Address Register Name: UDP_FADDR Address: 0x40034008 Access: Read-write – – – – – – – – – – – – – – – – – – – – – – – – FADD • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.

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