Atmel SAM4SD32B Preliminary Data Sheet page 1036

40.5.8 Fault Output
40.5.9 Conversion Performances
40.6 Functional Description
40.6.1 Analog-to-digital Conversion
Figure 40-2. Sequence of ADC conversions when Tracking time > Conversion time
ADCClock
Trigger event (Hard or Soft)
ADC_ON
Commands
ADC_Start
from controller
to analog cell
ADC_SEL
LCDR
DRDY
SAM4S Series [Preliminary]
1036
The ADC Controller has the FAULT output connected to the FAULT input of PWM. Please refer to
Section 40.6.13 "Fault Output"
For performance and electrical characteristics of the ADC, see the product DC Characteristics
section.
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 12-
bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the
Mode Register" on page 1049
the same register. The ADC Clock frequency is selected in the PRESCAL field of the Mode Reg-
ister (ADC_MR). The tracking phase starts during the conversion of the previous channel. If the
tracking time is longer than the conversion time, the tracking phase is extended to the end of the
previous conversion.
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to
255 (0xFF). PRESCAL must be programmed in order to provide an ADC clock frequency
according to the parameters given in the product Electrical Characteristics section.
CH0
Start Up Transfer Period
Time
(and tracking of CH0)
and implementation of the PWM in the product.
and Transfer Clock cycles as defined in the field TRANSFER of
CH1
CH0
Conversion Transfer Period
of CH0
Tracking of CH1
"ADC
CH2
CH1
Conversion
of CH1
Tracking of CH2
11100B–ATARM–31-Jul-12