Atmel SAM4SD32B Preliminary Data Sheet page 642

Figure 31-7. Status Register Flags Behavior
SPCK
NPCS0
MOSI
(from master)
TDRE
Write in
SPI_TDR
RDRF
MISO
(from slave)
TXEMPTY
SAM4S Series [Preliminary]
642
Figure 31-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg-
ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
1 2 3
MSB 6 5
MSB 6 5
Figure 31-8 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End
of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags
behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the
Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data.
The next pointer and counter are not used. The RDRF and TDRE are not shown because these
flags are managed by the PDC when using the PDC.
4 5 6 6
4 3 2
4 3 2
7 8
1 LSB
RDR read
1 LSB
shift register empty
11100B–ATARM–31-Jul-12