Figure 19-7. Example of Partial Page Programming
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Step 1.
Erase All Flash
So Page Y erased
19.4.3.3
Erase Commands
SAM4S Series [Preliminary]
334
Data are written to the latch buffer before the programming command is written to the Flash
Command Register EEFC_FCR. The sequence is as follows:
• Write the full page, at any page address, within the internal memory area address space.
• Programming starts as soon as the page number and the programming command are written
to the Flash Command Register. The FRDY bit in the Flash Programming Status Register
(EEFC_FSR) is automatically cleared.
• When programming is completed, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the corresponding interrupt line of the NVIC is activated.
Two errors can be detected in the EEFC_FSR register after a programming sequence:
• Command Error: a bad keyword has been written in the EEFC_FCR register.
• Lock Error: the page to be programmed belongs to a locked region. A command must be
previously run to unlock the corresponding region.
• Flash Error: at the end of the programming, the WriteVerify test of the Flash memory has
failed.
By using the WP command, a page can be programmed in several steps if it has been erased
before (see
Figure 19-7
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Programming of the second part of Page Y
Erase commands are allowed only on unlocked regions. Depending on the Flash memory, sev-
eral commands can be used to erase the Flash:
• Erase all memory (EA): all memory is erased. The processor must not fetch code from the
Flash memory.
• Erase pages (EPA): 4, 8, 16 or 32 pages are erased in the memory plane. The first page to
be erased is specified in the FARG[15:2] field of the MC_FCR register. The first page number
must be modulo 4, 8,16 or 32 according to the number of pages to erase at the same time.
The processor must not fetch code from the Flash memory.
below).
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Step 2.
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Step 3.
Programming of the third part of Page Y
11100B–ATARM–31-Jul-12
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