Event Send Control Register (Recr); Receive Area Refresh Register (Rdcr) - Hitachi HIDIC EH-150 Applications Manual

Event send Control Register (RECR)

Bit
15 14
- -
+H3
Bit 15-6: Reserved
These bits are reserved. Please set "0" always.
Bit 5-0: Event send request bit (ASE[6:1])
This bit works as an Event send request bit.
Bit5-0: ASE[6:1]
0 (1) Request to clear Transmit complete bit (TXC) of Connection n
(2) Event send is not done.
1 Request to execute Event sent to this module.
Automatic Receive mode control Register (EXRR)
Bit
15 14
- -
+H4
Bit 15-6: Reserved
These bits are reserved. Please set "0" always.
Bit 5-0: Automatic receive mode selective bit (ARP[6:1])
Bit5-0: ARP[6:1]
0 ASR connection n is selected Normal mode.
1 ASR connection n is selected Optional mode.

Receive area refresh Register (RDCR)

Bit
15 14
- -
+H5
Bit 15-6: Reserved
These bits are reserved bits. Please set "0" always.
Bit 5-0: Receive Ready bit (ARE[6:1])
This bit is effective to the connection which is declared as the connection on which Automatic Sending/Receiving
function is effective and Exclusive receive control set as enable. Therefore, this bit is ignored when the connection
which is declared as the other condition.
Bit5-0: ARE[6:1]
0 (1) Request to clear transmit complete bit (RXC) of Connection n
(2) The received data in the buffer of this module is not transmit to receive
1 Allow "Automatic Sending/Receiving function" to transmit data from
receive buffer in this module to receive area of CPU module.
13 12 11 10 9
- - - - -
communication status (CnCSR).
13 12 11 10 9
- - - - -
13 12 11 10 9
- - - - -
communication status (CnCSR).
area in CPU module. (This data is discarded in this module.)
8-9
Chapter 8 Register Structure
8 7 6 5 4
- - - ASE6 ASE5 ASE4 ASE3 ASE2 ASE1
Description
8 7 6 5 4
- - - ARP6 ARP5 ARP4 ARP3 ARP2 ARP1
Description
8 7 6 5 4
- - -
ARE6 ARE5 ARE4 ARE3 ARE2 ARE1
Description
3 2 1 0
(Initial set)
3 2 1 0
(Initial set)
3 2 1 0
(Initial set)