Connection N Error Status (Cnesr) - Hitachi HIDIC EH-150 Applications Manual

Connection n error status (CnESR) n = 1 to 6
Bit
15 14
- -
+H1
:
- -
+H6
The error condition of each connection (1 to 6) is shown in this area.
Bit 15-7: Reserved
These bits are reserved. Normally "0" is set.
Bit 6: ASR table set-up error bit (ATE[6:1])
These bits show the error condition of Automatic Sending/Receiving (ASR) table set-up.
Bit6: ATE[6:1]
0 No error is detected in ASR table set-up.
1 An error is detected in ASR table set-up.
Method to clear : To clear these bits to "0", please set the correct ASR table again.
Bit 5: Send error bit (SNE[6:1])
These bits are set below condition.
- At data send, there is a error of data transmission between EH-ETH and CPU module.
- A user program requires sending of data to EH-ETH before long EH-ETH has not completed the processing of
data sending.
When "send data error" occurs, data in the sending area in CPU module is guaranteed, but data in the sending
buffer in EH-ETH and receiving data at other station is not guaranteed.
Bit5: SNE[6:1]
0 No error is detected during the data sending.
1 An error is detected during the data sending,
Method to clear : To clear these bits to "0", please set "1" to SNC[6:1] of EC3CR.
Bit 4: Receive error bit (RCE[6:1])
These bits are set below condition.
- At data receiving, there is a error of data transmission between EH-ETH and CPU module.
- Before receiving buffer data is set to receiving area in CPU module, EH-ETH receive next data.
When receive error occurs, receiving area data in CPU module and receiving buffer data in EH-ETH and receiving
data at other station is not guaranteed.
Bit4: RCE[6:1]
0 No error is detected during the data receiving.
1 An error is detected during the data receiving.
Method to clear: To clear these bits to "0", please set "1" to RCC[6:1] of EC3CR.
Bit 3: Receive area error bit (RAE[6:1])
These bits show the receiving data size is more than allowed size or not.
Bit3: RAE[6:1]
0 Size of received data dose not exceed Receive area size.
1 Size of received data exceeds Receive area size.
Method to clear: To clear these bits to "0", please set "1" to RAC[6:1] of EC2CR.
Bit 2: Discard bit (DIS[6:1])
In case of optional mode in automatic receiving, if EH-ETH receives new coming data before the last data in the
buffer is refreshed, this bit will go high.
Bit2: DIS[6:1]
0 Received data has not been discarded.
1 Received data has been discarded.
Method to clear: To clear these bits to "0", please set "1" DIC[6:1] of EC2CR.
13 12 11 10 9
- - - - -
- - - - -
8-3
Chapter 8 Register Structure
8 7 6 5 4
- - ATE1 SNE1 RCE1
- - ATE6 SNE6 RCE6
Description
Description
Description
Description
Description
3 2 1 0
DIS1 STE1 OE1
RAE1
DIS6 STE6 OE6
RAE6