Hitachi HIDIC EH-150 Applications Manual page 91

Programable controller; ethernet module(eh-eth)
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[Basic operation 3]
To read status register (Control type "H0002"(handshake invalid))
R7E3
Wait execute
instruction
R7E4
Command execute
Command execute
R7E3
R7E4
Command execute
Wait execute
instruction
[Detect of command execution status]
When control type is "H0001" or "H0003" and you add the below two circuits just after FUN201 command
circuit, you can detect of command execution status.
R7E3
R7E4
R100 R101 R102
R100 R101 R102
R101 R102
Caution:
- During execution of command, when system area(s+1, s+2) of s parameter is changed, execution of
FUN201 command is not guaranteed.
- After execute flag set 1, FUN201 command is started to execute maximum 1 scan later.
- When execute flag is 0 and FUN201 is executed, read/write to the applied area is not execute.
st
1
scan
WR00B = H2
WR00C = H2F
ADRIO ( WR00D, R103 )
ADRIO ( WR00E, WM110 )
WR00F = 13
R103 = 1
FUN201 ( WR008 )
:
:
:
END
nd
2
scan
WR00B = H2
WR00C = H2F
ADRIO ( WR00D, R103 )
ADRIO ( WR00E, WM110 )
WR00F = 13
R103 = 1
FUN201 ( WR008 )
:
:
:
END
WR003 = H3
WR004 = H0
ADRIO ( WR005, R100 )
ADRIO ( WR006, WM100 )
WR007 = 10
R100 = 1
FUN201 ( WR000 )
R200
R201
R202
8-16
(00001)
(00002)
(00003)
- Next circuit is not executed before
completed of reading tatus register.
- After that, FUN201 clear execute flag.
- Set normal complete flag or abnormal
complete flag depend on the result of
execution.
(0000n)
(00001)
(00002)
(00003)
- Next circuit is not executed before
completed of reading tatus register.
- After that, FUN201 clear execute flag.
- Set normal complete flag or abnormal
complete flag depend on the result of
execution.
(0000n)
(00001)
(00002)
(00003)
R200 is ON: During Command execution
(00004)
(R200 = R100 && !R101 && !R102)
R201 is ON: Before command was completed
(00005)
normally and status of wait for instruction
(R201 = !R100 && R101 && !R102)
R202 is ON: Before command was completed
abnormally and status of wait for instruction
(R202 = !R100 && !R101 && R102)
Chapter 8 Register Structure

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