Quad-Spi Nor Flash; Quad-Spi Io Interface; Table 15. Hw Configuration For The Quad-Spi Interface; Table 16. Hw Configuration For The Quad-Spi Interface - ST STM32MP157 Series User Manual

6.12.1 NAND IO interface
Table 15 features the HW configuration for the NAND interface.
IO
PD6
PD11
PD12
PG9
PD5
PD4
PD14
PD15
PD0
PD1
PE7
PE8
PE9
PE10
1. Minimum set of signals required by the boot ROM during NAND boot in bold
6.13

Quad-SPI NOR Flash

The STM32MP157xAA3 Quad-SPI interface is in dual-Serial mode to interface with two NOR Flash memories in
parallel. Two MX25L51245G-XD, 3V3/512-Mbit each, are fitted on the STM32MP157x-EV1 MB1262, in
MB1262/U14 and MB1262/U15 positions.
6.13.1

Quad-SPI IO interface

Table 16 describes the HW configuration for the Quad-SPI interface
IO
PF8
PF9
PF7
PF6
PB6
PH2
PH3
PG10
PG7
PC0
PF10
UM2535 - Rev 1
Table 15. HW configuration for the Quad-SPI interface
NAND_NWAIT connected to MB1262/U11 R/B#
NAND_CLE connected to MB1262/U11 CLE
NAND_ALE connected to MB1262/U11 ALE
NAND_NCE connected to MB1262/U11 CE#
NAND_NWE connected to MB1262/U11 WE#
NAND_NOE connected to MB1262/U11 RE#
NAND_D0 connected to MB1262/U11 IO0
NAND_D1 connected to MB1262/U11 IO1
NAND_D2 connected to MB1262/U11 IO2
NAND_D3 connected to MB1262/U11 IO3
NAND_D4 connected to MB1262/U11 IO4
NAND_D5 connected to MB1262/U11 IO5
NAND_D6 connected to MB1262/U11 IO6
NAND_D7 connected to MB1262/U11 IO7
Table 16. HW configuration for the Quad-SPI interface
QSPI_BK1_IO0 connected to MB1262/U14 SIO0
QSPI_BK1_IO1 connected to MB1262/U14 SIO1
QSPI_BK1_IO2 connected to MB1262/U14 SIO2
QSPI_BK1_IO3 connected to MB1262/U14 SIO3
QSPI_BK1_NCS connected to MB1262/U14 CS#
QSPI_BK2_IO0 connected to MB1262/U15 SIO0
QSPI_BK2_IO1 connected to MB1262/U15 SIO1
QSPI_BK2_IO2 connected to MB1262/U15 SIO2
QSPI_BK2_IO3 connected to MB1262/U15 SIO3
QSPI_BK2_NCS connected to MB1262/U15 CS#
QSPI_CLK connected to MB1262/U14 SCLK and MB1262/U15 SCLK
(1)
Configuration
(1)
Configuration
UM2535
Quad-SPI NOR Flash
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