Ddr3L; Emmc; Emmc Io Interface; Nand Flash - ST STM32MP157 Series User Manual

Board function
Power
NJTRST
JTDI
JTMS/SWDIO
JTCK/SWCLK
Pull down
JTDO/SWO
NRST
Pull down
Pull down
6.10

DDR3L

Two 16-bit DDR3L NT5CC256M16ER-EK of 4 Gbytes are implemented in flyby topology in MB1263/U6 and U7
positions. They are connected to the dedicated DDR interface of STM32MP157xAA3. For detailed information
concerning the DDR HW design implementation, please refer to the application note AN5122 available on the
www.st.com website.
6.11

eMMC

The STM32MP157xAA3 SDMMC2 in 8-bit wide bus mode drives a THGBMNG5D1LBAIL 32 Gbits eMMC in
MB1263/U5 position.
6.11.1

eMMC IO interface

Table 14 HW configuration for the eMMC interface.
IO Configuration
PB14 SDMMC2_D0 connected to MB1263/U5 DAT0
PB15 SDMMC2_D1 connected to MB1263/U5 DAT1
PB3 SDMMC2_D2 connected to MB1263/U5 DAT2
PB4 SDMMC2_D3 connected to MB1263/U5 DAT3
PA8 SDMMC2_D4 connected to MB1263/U5 DAT4
PA9 SDMMC2_D5 connected to MB1263/U5 DAT5
PE5 SDMMC2_D6 connected to MB1263/U5 DAT6
PD3 SDMMC2_D7 connected to MB1263/U5 DAT7
PE3 SDMMC2_CK connected to MB1263/U5 CLK
PG6 SDMMC2_CMD connected to MB1263/U5 CMD
1. Minimum set of signals required by the boot ROM during eMMC boot in bold
6.12

NAND Flash

The STM32MP157xAA3 FMC interface is connected to an 8 Gbits SLC NAND, 8-bit, 8-bit ECC, and 4 KBytes PS
MT29F8G08ABACAH4 in MB1262/U11 position.
UM2535 - Rev 1
Table 13. MB1262/CN14 JTAG connector pinout
Pin
1
3
5
7
9
11
13
15
17
19
Table 14. HW configuration for the Quad-SPI interface
(1)
Pin Board function
2 Power
4 GND
6 GND
8 GND
10 GND
12 GND
14 GND
16 GND
18 GND
20 GND
UM2535
DDR3L
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