Factory Default Switch Settings - Altera Cyclone V GX FPGA User Manual

4–2
f
For more information about the PFL megafunction, refer to
Megafunction User

Factory Default Switch Settings

This section shows the factory switch settings
FPGA development board.
Figure 4–1. Switch Locations and Default Settings
SW3
To restore the switches to their factory default settings, perform these steps:
1. Set the DIP switch bank (SW3) to match
Table 4–1. SW3 DIP Switch Settings (Part 1 of 2)
Switch
1
2
Cyclone V GX FPGA Development Kit
User Guide
Guide.
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
-
FAN_FORCE_ON
CLK SEL
CLK EN
FACT LOAD
SEC MODE
Off On
Board
Label
Switch 1 has the following options:
■
CLK SEL
■
Switch 2 has the following options:
CLK EN
■
■
(Figure 4–1) for the Cyclone V GX
SW4 SW5
5M2210_JTAG_EN
HSMA_JTAG_EN
PCIE_JTAG_EN
-
Off On
On
Off
Table 4–1 and
Function
On (0) = SMA input clock is selected.
Off (1) = Programmable oscillator clock is
selected.
On (0) = On-board oscillator is disabled.
Off (1) = On-board oscillator is enabled.
Chapter 4: Development Board Setup
Factory Default Switch Settings
Parallel Flash Loader
Figure 4–1.
Default
Position
Off
Off
October 2012 Altera Corporation