Altera Cyclone V GX FPGA User Manual page 13

Chapter 4: Development Board Setup
Factory Default Switch Settings
Table 4–1. SW3 DIP Switch Settings (Part 2 of 2)
Switch
3
4
2. Set the DIP switch bank (SW4) to match
Table 4–2. SW4 DIP Switch Settings
Switch
1
2
3
4
3. Set the DIP switch bank (SW5) to match
Table 4–3. SW5 JTAG DIP Switch Settings (Part 1 of 2)
Switch
1
2
October 2012 Altera Corporation
Board
Label
Switch 3 has the following options:
On (0) = Load the user design from flash at
■
FACT LOAD power up.
Off (1) = Load the user factory from flash at
■
power up.
Switch 4 has the following options:
On (0) = On-Board USB Blaster II sends
■
SEC MODE FACTORY command at power up
Off (1) = On-Board USB Blaster II does not
■
send FACTORY command at power up
Board
Label
Switch 1 has the following options:
PCIE_PRSNT2n_x1 On (0) = x1 presence detect is enabled.
■
Off (1) = x1 presence detect is disabled.
■
Switch 2 has the following options:
PCIE_PRSNT2n_x4 On (0) = x4 presence detect is enabled.
■
Off (1) = x4 presence detect is disabled.
■
— —
Switch 4 has the following options: (Fan is not
included.)
FAN_FORCE_ON
On (0) = Fan is turned on.
■
Off (1) = Fan is turned off
■
Board
Label
Switch 1 has the following options:
On (0) = Do not Include MAX V system
■
5M2210_JTAG_EN controller in the JTAG chain.
Off (1) = Include MAX V system controller in
■
the JTAG chain
Switch 2 has the following options:
On (0) = Do not Include the HSMC Port A in the
■
HSMA_JTAG_EN JTAG chain.
Off (1) = Include the HSMC Port A in the JTAG
■
chain.
Function
Table 4–2 and Figure 4–1.
Function
Table 4–3 and Figure 4–1.
Function
Cyclone V GX FPGA Development Kit
4–3
Default
Position
Off
Off
Default
Position
Off
Off
—
Off
Default
Position
Off
On
User Guide