Counter Timing Engine; Counter Timing Measurements - National Instruments NI cRIO-905x Series User Manual

Embedded compactrio controller with real-time processor and reconfigurable fpga
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Counter Timing Engine

Unlike analog input, analog output, digital input, and digital output, the cRIO controller
counters do not have the ability to divide down a timebase to produce an internal counter
sample clock. For sample clocked operations, an external signal must be provided to supply a
clock source. The source can be any of the following signals:
AI Sample Clock
AI Start Trigger
AI Reference Trigger
AO Sample Clock
DI Sample Clock
DI Start Trigger
DO Sample Clock
CTR n Internal Output
Freq Out
PFI
Change Detection Event
Analog Comparison Event
Not all timed counter operations require a sample clock. For example, a simple buffered pulse
width measurement latches in data on each edge of a pulse. For this measurement, the
measured signal determines when data is latched in. These operations are referred to as
implicit timed operations. However, many of the same measurements can be clocked at an
interval with a sample clock. These are referred to as sample clocked operations. The
following table shows the different options for the different measurements.
Measurement
Buffered Edge Count
Buffered Pulse Width
Buffered Pulse
Buffered Semi-Period
Buffered Frequency
Buffered Period
64 | ni.com | NI cRIO-905x User Manual
Table 17. Counter Timing Measurements
Implicit Timing Support
Sample Clocked Timing
No
Yes
Yes
Yes
Yes
Yes
Support
Yes
Yes
Yes
No
Yes
Yes

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