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National Instruments DAQ-STC Series Technical Reference Manual

National Instruments DAQ-STC Series Technical Reference Manual (555 pages)

System Timing Controller for Data Acquisition

Brand: National Instruments | Category: Controller | Size: 3 MB

Table of Contents

Table of Contents

4
Table of Contents

17
- About this Manual
  21
- Chapter 1 Introduction
  
  26
  - DAQ-STC Applications
    27
    
    Analog Input Application
    27
- Appendix C
  
  27
- Appendix D
  
  27
- Appendix E
  
  27
  - Figure 1-1. Analog Input Application
    27
  - Analog Output Application
    28
  - Figure 1-2. Analog Output Application
    28
  - DAQ-STC Block Diagram
    29
  - Figure 1-3. DAQ-STC Block Diagram
    29
  - Chapter 2 Analog Input Timing/Control
    
    30
    
    Overview
    30
    
    Programming the AITM
    30
    
    Features
    31
    
    Figure 2-1. Typical Analog Input Waveform
    33
    
    Simplified Model
    33
    
    Figure 2-2. AITM Simplified Model
    34
    
    Analog Input Functions
    35
    
    Low-Level Timing and Control
    35
    
    ADC Control
    36
    
    Configuration FIFO and External Multiplexer Control
    36
    
    Data FIFO Control
    36
    
    Figure 2-3. ADC Control
    36
    
    Figure 2-4. Configuration FIFO Control
    37
    
    CONVERT Timing
    38
    
    Figure 2-5. External Multiplexer Control
    38
    
    Figure 2-6. Internal CONVERT Timing
    39
    
    Figure 2-7. External CONVERT Timing
    40
    
    Internal START Mode
    40
    
    Scan-Level Timing and Control
    40
    
    External START Mode
    41
    
    Figure 2-8. Internal START
    41
    
    Figure 2-10. si Special Trigger Delay
    42
    
    Figure 2-9. External START
    42
    
    Acquisition-Level Timing and Control
    43
    
    Figure 2-11. Posttrigger Acquisition Mode
    43
    
    Posttrigger Acquisition Mode
    43
    
    Pretrigger Acquisition Mode
    43
    
    Continuous Acquisition Mode
    44
    
    Figure 2-12. Pretrigger Acquisition Mode
    44
    
    Gating
    45
    
    Master/Slave Trigger
    45
    
    Staged Acquisition
    45
    
    Figure 2-13. Free-Run Gating Mode
    46
    
    Free-Run Gating Mode
    46
    
    Halt-Gating Mode
    46
    
    Figure 2-14. Halt-Gating Mode
    47
    
    Figure 2-15. Single-Wire Mode
    47
    
    Single-Wire Mode
    47
    
    Pin Locator Interface
    48
    
    Table 2-1. Pin Interface
    48
    
    Programming Information
    53
    
    Register and Bitfield Programming Considerations
    53
    
    Programming for an Analog Input Operation
    54
    
    Windowing Registers
    54
    
    Resetting
    55
    
    Board Power-Up Initialization
    56
    
    Initialize Configuration Memory Output
    57
    
    Board Environment Setup
    58
    
    FIFO Request
    59
    
    Hardware Gate Programming
    59
    
    Software Gate Operation
    60
    
    Trigger Signals
    61
    
    Number of Scans
    62
    
    Start of Scan
    63
    
    End of Scan
    66
    
    Convert Signal
    67
    
    Enable Interrupts
    69
    
    Arming
    70
    
    Starting the Acquisition
    70
    
    Analog Input Program
    71
    
    Single Scan
    71
    
    Change Scan Rate During an Acquisition
    72
    
    Staged Acquisition
    73
    
    Master/Slave Operation Considerations
    74
    
    Analog Input-Related Interrupts
    75
    
    Bitfield Descriptions
    77
    
    Convert_Src
    113
    
    Signal Definitions
    113
    
    Table 2-2. CONVERT_SRC Reference Pin Selection
    113
    
    Timing Diagrams
    113
    
    Out_Clk
    114
    
    Basic Analog Input Timing
    115
    
    Figure 2-16. Basic Analog Input Timing
    115
    
    Table 2-3. Basic Analog Input Timing
    115
    
    Data Fifos
    117
    
    Figure 2-17. Data FIFO Timing
    117
    
    Configuration Memory
    118
    
    Figure 2-18. Configuration Memory Timing
    118
    
    Table 2-4. Configuration Memory Timing
    119
    
    Maximum Rate Analog Input
    120
    
    External CONVERT Source
    121
    
    Figure 2-19. Maximum Rate Analog Input Timing
    121
    
    External Triggers
    122
    
    Figure 2-21. External Trigger Timing, Asynchronous Level
    123
    
    Figure 2-23. External Trigger Timing, Synchronous Level Internal CONVERT Mode
    124
    
    Figure 2-25. External Trigger Timing, Synchronous Level External CONVERT Mode
    125
    
    Table 2-5. External Analog Input Timing
    125
    
    START1 and START2 Triggers
    126
    
    Trigger Output
    126
    
    Figure 2-27. START1 Delays, Synchronous Mode, Internal CONVERT
    127
    
    Figure 2-30. START2 Delays, Synchronous Mode, External CONVERT
    128
    
    Table 2-6. START1 and START2 Timing, Synchronous Mode
    128
    
    START Trigger and SCAN_IN_PROG Assertion
    129
    
    Table 2-7. START1 and START2 Timing, Asynchronous Mode
    129
    
    Figure 2-33. START Delays, Internal CONVERT
    130
    
    Figure 2-34. START Delays, External CONVERT
    131
    
    SCAN_IN_PROG Deassertion
    132
    
    STOP Trigger
    132
    
    Figure 2-36. STOP Delay, Synchronous Mode
    133
    
    Counter Outputs
    134
    
    Sc_Tc
    134
    
    Si_Tc
    134
    
    Div_Tc
    135
    
    Macro-Level Analog Input Timing
    135
    
    Table 2-8. Interval Scanning Mode Timing
    136
    
    External Gating
    138
    
    Figure 2-43. Free-Run Gating Mode Timing, External CONVERT
    139
    
    Figure 2-44. Halt-Gating Mode Timing, Internal CONVERT
    140
    
    Detailed Description
    141
    
    Internal Signals and Operation
    142
    
    Table 2-9. Internal Signals
    142
    
    Trigger Selection and Conditioning
    148
    
    Figure 2-46. START and STOP Routing Logic
    149
    
    Figure 2-48. EXT_GATE Routing Logic
    150
    
    Table 2-10. PFI Selectors
    150
    
    Trigger Signals
    151
    
    Using Edge Detection
    151
    
    Using Synchronization
    151
    
    Analog Input Counters
    152
    
    SC Control
    153
    
    SC Counter
    153
    
    Figure 2-49. SC Control Circuit State Transitions
    154
    
    SI Control
    155
    
    SI Counter
    155
    
    SI2 Control
    156
    
    SI2 Counter
    156
    
    DIV Counter
    157
    
    DIV Control
    158
    
    Interrupt Control
    159
    
    Table 2-11. Analog Input Interrupts
    160
    
    Error Detection
    161
    
    Overflow Error
    161
    
    Overrun Error
    161
    
    SC_TC Error
    161
    
    Nominal Signal Pulsewidths
    162
    
    Table 2-12. Analog Input Nominal Signal Widths
    162
    
    Overview
    163
    
    Features
    164
    
    Programming the AOTM
    164
    
    Simplified Model
    166
    
    Analog Output Functions
    167
    
    Primary Group Analog Output Modes
    167
    
    CPU-Driven Analog Output
    168
    
    DAQ-STC-Driven Analog Output
    168
    
    DAQ-STC and CPU Conflict
    169
    
    Figure 3-3. CPU-Driven Analog Output
    169
    
    DAC Interface
    170
    
    Data Interfaces
    170
    
    FIFO Data Interface
    170
    
    Figure 3-5. FIFO Data Interface
    171
    
    Serial Link Data Interface
    172
    
    Internal UPDATE
    173
    
    Unbuffered Data Interface
    173
    
    Update Timing for Primary Group Analog Output
    173
    
    Buffer Timing and Control for Primary Analog Output
    174
    
    External UPDATE
    174
    
    Continuous Mode
    175
    
    Single-Buffer Mode
    175
    
    Waveform Staging
    176
    
    Master/Slave Trigger
    177
    
    Mute Buffers
    177
    
    Secondary Analog Output
    178
  - Chapter 3 Analog Output Timing/Control
    
    163
    
    Pin Interface
    178
    
    Programming for a Primary Analog Output Operation
    182
    
    Programming Information
    182
    
    Overview
    183
    
    Resetting
    183
    
    Board Power-Up Initialization
    184
    
    Trigger Signals
    185
    
    Number of Buffers
    186
    
    Update Selection
    188
    
    Channel Select
    190
    
    FIFO Mode
    191
    
    LDAC Source and UPDATE Mode
    191
    
    Stop on Error
    191
    
    Arming
    192
    
    Enable Interrupts
    192
    
    Primary Analog Output Program
    193
    
    Starting the Waveform
    193
    
    Waveform Staging for Primary Analog Output
    194
    
    Changing Update Rate During an Output Operation for Primary Analog Output Group
    196
    
    Master/Slave Operation Considerations for Primary Analog
    197
    
    Output Group
    197
    
    Primary Analog Output Group-Related Interrupts
    197
    
    Overview
    200
    
    Programming for a Secondary Analog Output Group Operation
    200
    
    Resetting
    200
    
    Board Power-Up Initialization
    201
    
    Hardware Gate Programming
    201
    
    Counting for Waveform Staging
    202
    
    Software Gate Operation
    202
    
    Update Selection
    202
    
    Arming
    203
    
    Secondary Analog Output Program
    203
    
    Waveform Staging for Secondary Analog Output
    204
    
    Changing Update Rate During an Output Operation for Secondary Analog Output
    206
    
    Bitfield Descriptions
    207
    
    Master/Slave Operation Considerations for Secondary Analog Output
    207
    
    Secondary Analog Output-Related Interrupts
    207
    
    Signal Definitions
    246
    
    Timing Diagrams
    246
    
    Table 3-2. UPDATE_SRC Reference Pin Selection
    247
    
    Table 3-3. UI2_SRC Reference Pin Selection
    247
    
    Out_Clk
    248
    
    Table 3-4. DAQ-STC-Driven Analog Output Timing
    248
    
    Figure 3-14. DAQ-STC-Driven Analog Output Timing
    249
    
    CPU-Driven Analog Output Timing
    250
    
    Figure 3-15. CPU-Driven Analog Output Timing
    251
    
    DAQ-STC- and CPU-Driven Analog Output Timing
    252
    
    Figure 3-16. Analog Output Contention Timing, Case a
    253
    
    Figure 3-17. Analog Output Contention Timing, Case B
    254
    
    Secondary Analog Output Timing
    255
    
    Decoded Signal Timing
    256
    
    Figure 3-19. Decoded Signal Timing
    257
    
    Local Buffer Mode Timing
    258
    
    Figure 3-20. Local Buffer Mode Timing
    259
    
    Unbuffered Data Interface Timing
    260
    
    Figure 3-21. Unbuffered Data Interface Timing
    261
    
    Maximum Update Rate Timing
    263
    
    External Trigger Timing
    264
    
    Figure 3-25. External Trigger, Synchronous Level, Internal UPDATE Mode
    265
    
    START1 Trigger
    266
    
    Table 3-5. External Trigger Timing
    266
    
    Trigger Output
    266
    
    Figure 3-29. START1 Delays, Synchronous Mode, Internal UPDATE
    267
    
    Figure 3-30. START1 Delays, Synchronous Mode, External UPDATE
    268
    
    Bc_Tc
    269
    
    Counter Outputs
    269
    
    Detailed Description
    270
    
    Uc_Tc
    270
    
    Internal Signals and Operation
    271
    
    Table 3-6. Internal Signals
    271
    
    Trigger Selection and Conditioning
    276
    
    Figure 3-35. START1 Routing Logic
    277
    
    Trigger Signals
    278
    
    Using Edge Detection
    278
    
    Using Synchronization
    278
    
    Analog Output Counters
    279
    
    UI Counter
    279
    
    UC Counter
    280
    
    UI Control
    280
    
    UC Control
    281
    
    BC Control
    282
    
    BC Counter
    282
    
    UI2 Counter
    283
    
    Interrupt Control
    284
    
    Table 3-8. Analog Output Interrupts
    284
    
    Output Control
    285
    
    Nominal Signal Pulsewidths
    286
    
    Table 3-9. Analog Output Nominal Signal Widths
    286
    
    Overview
    287
    
    Simplified Model
    288
  - Chapter 4 General-Purpose Counter/Timer
    
    289
    
    Counter/Timer Functions
    289
    
    Figure 4-2. Simple Event Counting
    290
    
    Figure 4-4. Buffered Noncumulative Event Counting
    291
    
    Time Measurement
    292
    
    Figure 4-7. Single-Period Measurement
    293
    
    Figure 4-9. Buffered Period Measurement
    294
    
    Pulse Generation
    295
    
    Figure 4-12. Single Pulse Generation
    296
    
    Figure 4-14. Retriggerable Single Pulse Generation
    297
    
    Pulse-Train Generation
    298
    
    Figure 4-16. Continuous Pulse-Train Generation
    299
    
    Figure 4-18. Buffered Pulse-Train Generation
    300
    
    Figure 4-19. Frequency Shift Keying
    301
    
    Table 3-1. Pin Interface
    302
    
    Programming Information
    303
    
    Notation
    304
    
    Simple Event Counting
    305
    
    Buffered Event Counting
    306
    
    Relative Position Sensing
    309
    
    Single-Period and Pulsewidth Measurement
    310
    
    Buffered Period, Semiperiod, and Pulsewidth Measurement
    312
    
    Pulse and Continuous Pulse-Train Generation
    314
    
    Frequency Shift Keying
    317
    
    Pulse-Train Generation for ETS
    319
    
    Reading the Counter Contents
    320
    
    Enabling the General Purpose Counter/Timer Output Pin
    321
    
    Timing Diagrams
    339
    
    Table 4-2. CTRGATE Reference Pin Selection
    340
    
    CTRSRC Minimum Period and Minimum Pulsewidth
    341
    
    G_GATE Minimum Pulsewidth
    342
    
    CTRGATE to CTROUT Delay
    343
    
    CTRGATE Setup
    344
    
    CTR_U/D Setup
    345
    
    Figure 4-28. CTR_U/D Setup Timing, Internal Timing Mode
    346
    
    Detailed Description
    347
    
    Internal Signals and Operation
    348
    
    G_SOURCE Selection and Conditioning
    349
    
    G_GATE Selection and Conditioning
    350
    
    G_OUT Conditioning and Routing
    351
    
    Table 4-12. G_OUT0/RTSI_IO Selection
    352
    
    G_CONTROL Conditioning
    353
    
    START/STOP on G_CONTROL
    354
    
    UP/DOWN on G_CONTROL
    355
    
    Interrupt Control
    356
    
    Table 3-7. PFI Selectors
    356
    
    Error Detection
    357
    
    Detailed Operation by Application
    358
    
    Figure 4-32. Simple Event Counting
    359
    
    Figure 4-34. Buffered Noncumulative-Event Counting
    360
    
    Figure 4-35. Buffered Cumulative-Event Counting
    361
    
    Figure 4-37. Single-Period Measurement
    362
    
    Figure 4-38. Single Pulsewidth Measurement
    363
    
    Figure 4-39. Buffered Period Measurement
    364
    
    Figure 4-40. Buffered Semiperiod Measurement
    365
    
    Figure 4-41. Buffered Pulsewidth Measurement
    366
    
    Figure 4-42. Single Pulse Generation
    367
    
    Figure 4-43. Single-Triggered Pulse Generation
    368
    
    Figure 4-44. Retriggerable Single Pulse Generation
    369
    
    Figure 4-45. Continuous Pulse-Train Generation
    370
    
    Figure 4-46. Buffered Pulse-Train Generation
    371
    
    Figure 4-47. Frequency Shift Keying
    372
    
    Figure 4-48. Pulse Generation for ETS
    373
    
    Overview
    374
    
    Pin Interface
    375
    
    Programming Information
    378
    
    Bitfield Descriptions
    379
    
    Detailed Description
    380
    
    Table 5-3. PFI<0..9> Output Selections
    381
    
    Overview
    383
    
    Programming Information
    384
    
    Bitfield Descriptions
    385
    
    Detailed Description
    388
    
    Table 6-3. RTSI_BRD<0..1> Output Selections
    389
    
    Overview
    390
    
    Overview of DIO Functions
    391
    
    Parallel Input
    392
    
    Serial Output
    393
  - Chapter 7 Digital I/O
    
    393
    
    Serial Mode
    393
    
    Serial I/O
    394
    
    Pin Interface
    395
    
    Programming Information
    396
    
    Programming the Digital Interface
    397
    
    Parallel Digital I/O
    398
    
    Hardware-Controlled Serial Digital I/O
    399
    
    Software-Controlled Serial Digital I/O
    401
    
    Bitfield Descriptions
    402
    
    Serial Input Timing
    404
    
    Timing Diagrams
    404
    
    Serial Output Timing
    405
    
    Detailed Description
    406
  - Chapter 8 Interrupt Control
    
    407
    
    Overview
    407
    
    Pin Interface
    408
    
    Programming Information
    409
    
    Interrupt Handling
    411
    
    Bitfield Descriptions
    418
    
    Interrupt Conditions
    421
  - Chapter 10 Miscellaneous Functions
    
    423
    
    Overview
    423
    
    Table 9-1. Pin Interface
    424
    
    Programming Information
    425
  - Chapter 9 Bus Interface
    
    426
    
    Programming the Write Strobes
    426
    
    Timing Diagrams
    427
    
    Figure 9-1. Intel Bus Interface Read Timing
    428
    
    Intel Bus Interface Write Timing
    428
    
    Figure 9-3. Motorola Bus Interface Read Timing
    429
    
    Figure 9-4. Motorola Bus Interface Write Timing
    430
    
    Overview
    431
    
    Clock Distribution
    432
    
    Frequency Output
    433
    
    Figure 10-2. Low-Window Mode
    434
    
    Figure 10-4. Middle-Window Mode
    435
    
    Test Mode
    436
    
    Figure 10-7. Test Mode Internal Gate Tree
    437
    
    Table 10-2. Test Mode Input Pin Pairs
    438
    
    Pin Interface
    439
    
    Programming Information
    440
    
    Programming FOUT
    442
    
    Table B-1. DAQ-STC Registers
    450
    
    Table B-2. Registers in Order of Address*
    454
    
    Table B-3. Bitfield Description Guide
    458
    
    Table C-1. DAQ-STC Pins in Alphabetical Order
    488
    
    Table C-2. Summary of Buffer Types
    494

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