Clock Routing; 80 Mhz Timebase - National Instruments NI cRIO-905x Series User Manual

I/O, and counters. The digital routing circuitry uses FIFOs (if present) in each sub-system to
ensure efficient data movement.
Note
When programming C Series modules in FPGA mode, the flow of data
between the modules and the bus interface is programmed using LabVIEW FPGA.
The digital routing circuitry also routes timing and control signals. The acquisition and
generation sub-systems use these signals to manage and synchronize acquisitions and
generations. These signals can come from the following sources:
• C Series modules programmed in Real-Time (NI-DAQmx) mode
• User input through the PFI terminals using parallel digital C Series modules or the
cRIO-905x PFI 0 terminal
• FPGA or DAQ ASIC using the cRIO trigger bus to share hardware triggers and signals
between the LabVIEW FPGA and DAQmx applications

Clock Routing

The following figure shows the clock routing circuitry of the cRIO-905x.
Onboard
100 MHz
Oscillator
Note
When switching between programming modes, you may notice the terms
timebase and clock used interchangeably. This is due to the DAQ ASIC and the RIO
FPGA using different terminology for timing and clock mechanisms. The
documentation will use the term based on the programming mode discussed.

80 MHz Timebase

When programming C Series modules in Real-Time (NI-DAQmx) mode, the 80 MHz
timebase can function as the source input to the 32-bit general-purpose counter/timers. The
80 MHz timebase is generated from the onboard oscillator.
Figure 6. Clock Routing Circuitry of the cRIO-905x
Clock
Generator
DAQ ASIC
80 MHz Timebase
÷4 20 MHz Timebase
÷200 100 kHz Timebase
13.1072 MHz Timebase
12.8 MHz Timebase
10 MHz Timebase
cRIO Trigger Bus
RIO FPGA
÷2 40 MHz Onboard Clock
13.1072 MHz Carrier Clock
12.8 MHz Carrier Clock
10 MHz Carrier Clock
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