Audio Interface - Renesas RTK79210**B00000BE User Manual

Sub board, rz family / rz/a series
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RZ/A2M SUB Board RTK79210XXB00000BE
2.10

Audio Interface

RTK79210XXB00000BE is equipped with a Cirrus audio CODEC WM8978 × 1 for audio interface. The WM8978
register control is performed on the channel 0 of the RZ/A2M on-chip Renesas serial peripheral interface (RSPI), and the
input/output control for audio data is performed on the channel 0 of the RZ/A2M on-chip serial sound interface (SSIF-2).
Figure 2.10.1 shows the audio interface block diagram, and Table 2.10.1 shows the function setting table of DIP
switches SW6-1 and SW6-2 for system setting.
RZ/A2M (U1)
P8_7
P8_7 / A7 / DRP17 /
RSPCK0
P8_4
P8_4 / A4 / DRP20 /
SSL00
P8_6
P8_6 / A6 / DRP18 /
MOSI0
P9_6
P9_6 / A14 / DRP10 /
SSIBCK0
P9_5
P9_5 / A13 / DRP11 /
SSIFS0
P9_4
P9_4 / A12 / DRP12 /
SSITxD0
P9_3
P9_3 / A11 / DRP13 /
SSIRxD0
P6_4
P6_4 / DRP00 /
AUDIO_CLK
Note:
Red text
indicates a function used.
:Indicates a function not implemented .
:Indicates a SUB board.
Figure 2.10.1
Audio Interface Block Diagram
Table 2.10.1
Function Setting Table of DIP Switches SW6-1 and SW6-2 for System Setting
DIP
switch
SW6-1
P8_4 and P8_[7 :6], P9_[6 :3] are used as SDRAM
control pins.
SW6-2
P8_4 and P8_[7 :6], P6_4, P9_[6 :3] are used as
DRP pins.
[Note]
indicates setting functions.
R20UT4398EJ0100 Rev.1.00
2018.10.11
8
SDRAM / Other(Audio)(U5)
1B1
P8_4
1A
P8_4
1B2
3B1
P8_6
3A
P8_6
3B2
4B1
P8_7
4A
P8_7
4B2
OE#
MUX
S
SDRAM / Other(Audio)(U8)
4B1
P9_3
4A
P9_3
4B2
OE#
MUX
S
SDRAM / Other(Audio)(U10)
1B1
P9_4
1A
P9_4
1B2
2B1
P9_5
2A
P9_5
2B2
3B1
P9_6
3A
P9_6
3B2
OE#
MUX
S
ON(L):A=B1, OFF(H):A=B2
3.3V
DIP
SW6-1
OFF
P6_4
ON
7
To SDRAM
8
8
DRP / Audio(U3)
1B1
P8_4
1A
SSL
1B2
2B1
P8_6
2A
MOSI
2B2
3B1
P8_7
3A
RSPCK
3B2
4B1
P6_4
4A
CLK
4B2
OE#
MUX
S
DRP / Audio(U6)
1B1
P9_3
1A
SSIRxD
1B2
2B1
P9_4
2A
SSITxD
2B2
3B1
P9_5
3A
SSIFS
3B2
4B1
P9_6
4A
SSIBCK
4B2
OE#
MUX
S
ON(L):A=B1, OFF(H):A=B2
3.3V
DIP
SW6-2
OFF
Function
P8_4 and P8_[7 :6], P9_[6 :3] are used as audio
interface pins (default settings).
P8_4 and P8_[7 :6], P6_4, P9_[6 :3] used as audio
interface pins (default settings).
2. Function specifications
8
To DRP I/F
3.3V
3.3V
Audio CODEC(U21)
3.3V
RSPCK
SCLK
MODE
3.3V
SSL
CSB/GPIO1
3.3V
MOSI
SDIN
L2/GPIO2
3.3V
SSIBCK
BCLK
MICBIAS
3.3V
SSIFS
LRC
R2/GPIO3
SSITxD
+
DACDAT
LOUT1
SSIRxD
ADCDAT
CLK
+
ROUT1
Socket(X1)
CLK
MCLK
11.2896MHz
OFF
+
CN3
CN4
2-33

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