Prcm Registers - Texas Instruments CC3200 Technical Reference Manual

PRCM Registers

15.7 PRCM Registers
Table 15-3 lists the memory-mapped registers for the ARCM. All register offset addresses not listed in
Table 15-3 should be considered as reserved locations, and the register contents should not be modified.
Offset Acronym
0h CAMCLKCFG
4h CAMCLKEN
8h CAMSWRST
14h MCASPCLKEN
18h MCASPSWRST
20h SDIOMCLKCFG
24h SDIOMCLKEN
28h SDIOMSWRST
2Ch APSPICLKCFG
30h APSPICLKEN
34h APSPISWRST
48h DMACLKEN
4Ch DMASWRST
50h GPIO0CLKEN
54h GPIO0SWRST
58h GPIO1CLKEN
5Ch GPIO1SWRST
60h GPIO2CLKEN
64h GPIO2SWRST
68h GPIO3CLKEN
6Ch GPIO3SWRST
70h GPIO4CLKEN
74h GPIO4SWRST
78h WDTCLKEN
7Ch WDTSWRST
80h UART0CLKEN
84h UART0SWRST
88h UART1CLKEN
8Ch UART1SWRST
90h GPT0CLKCFG
94h GPT0SWRST
98h GPT1CLKEN
9Ch GPT1SWRST
A0h GPT2CLKEN
A4h GPT2SWRST
A8h GPT3CLKEN
ACh GPT3SWRST
B0h MCASPCLKCFG0
B4h MCASPCLKCFG1
D8h I2CLCKEN
DCh I2CSWRST
E4h LPDSREQ
ECh TURBOREQ
108h DSLPWAKECFG
470
Power, Reset and Clock Management
Table 15-3. PRCM Registers
Register Name
Copyright © 2014–2018, Texas Instruments Incorporated
Section
Section 15.7.1.1
Section 15.7.1.2
Section 15.7.1.3
Section 15.7.1.4
Section 15.7.1.5
Section 15.7.1.6
Section 15.7.1.7
Section 15.7.1.8
Section 15.7.1.9
Section 15.7.1.10
Section 15.7.1.11
Section 15.7.1.12
Section 15.7.1.13
Section 15.7.1.14
Section 15.7.1.15
Section 15.7.1.16
Section 15.7.1.17
Section 15.7.1.18
Section 15.7.1.19
Section 15.7.1.20
Section 15.7.1.21
Section 15.7.1.22
Section 15.7.1.23
Section 15.7.1.24
Section 15.7.1.25
Section 15.7.1.26
Section 15.7.1.27
Section 15.7.1.28
Section 15.7.1.29
Section 15.7.1.30
Section 15.7.1.31
Section 15.7.1.32
Section 15.7.1.33
Section 15.7.1.34
Section 15.7.1.35
Section 15.7.1.36
Section 15.7.1.37
Section 15.7.1.38
Section 15.7.1.39
Section 15.7.1.40
Section 15.7.1.41
Section 15.7.1.42
Section 15.7.1.43
Section 15.7.1.44
SWRU367D – June 2014 – Revised May 2018
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