Adc_Ch6_Irq_Status Register - Texas Instruments CC3200 Technical Reference Manual

ADC_MODULE Registers
13.4.1.9 ADC_CH6_IRQ_STATUS Register (offset = 5Ch) [reset = 0h]
ADC_CH6_IRQ_STATUS is shown in
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3-0 ADC_CHANNEL6_IRQ_S
TATUS
408
Analog-to-Digital Converter [ADC]
Figure 13-11
Figure 13-11. ADC_CH6_IRQ_STATUS Register
29 28
21 20
13 12
5 4
R-0h
Table 13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2014–2018, Texas Instruments Incorporated
and described in Table
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
ADC_CHANNEL6_IRQ_STATUS
Description
Interrupt status register for ADC channel. Interrupt status can be
cleared on write.
Bit 3: when value 1 is written -> Clears FIFO overflow interrupt status
in the next cycle. If the same interrupt is set in the same cycle, then
the interrupt would be set and the clear command ignored.
Bit 2: when value 1 is written -> Clears FIFO underflow interrupt
status in the next cycle.
Bit 1: when value 1 is written -> Clears FIFO empty interrupt status
in the next cycle.
Bit 0: when value 1 is written -> Clears FIFO full interrupt status in
the next cycle.
13-11.
26 25
18 17
10 9
2 1
R/W-0h
SWRU367D – June 2014 – Revised May 2018
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16
8
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