Peripheral Interface - Texas Instruments CC3200 Technical Reference Manual

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4.2.7 Peripheral Interface

There are two main classes of µDMA-connected peripherals:
• Peripherals with FIFOs serviced by the µDMA to transmit or receive data
• Peripherals that provide trigger inputs to the µDMA
4.2.7.1 FIFO Peripherals
FIFO peripherals contain a FIFO of data to be sent and a FIFO of data that has been received. The µDMA
controller transfers data between these FIFOs and system memory. For example, when a UART FIFO
contains one or more entries, a single transfer request is sent to the µDMA for processing. If this request
has not been processed and the UART FIFO reaches the interrupt FIFO level, another interrupt is sent to
the µDMA which is higher priority than the single-transfer request. In this instance, an ARBSIZ transfer is
performed as configured in the DMACHCTL register. After the transfer is complete, the µDMA sends a
receive or transmit complete interrupt to the UART register.
If the SETn bit of the FIFO peripheral is set in the DMA Channel Useburst Set (DMAUSEBURSTSET)
register, then the µDMA only performs transfers defined by the ARBSIZ bit field in the DMACHCTL
register for better bus utilization. For peripherals that tend to transmit and receive in bursts, such as the
UART, TI recommends against the use of this configuration because it could cause the tail end of
transmissions to stick in the FIFO.
4.2.7.2 Trigger Peripherals
Certain peripherals, such as the general purpose timer, trigger an interrupt to the µDMA controller when a
programmed event occurs. When a trigger event occurs, the µDMA executes a transfer defined by the
ARBSIZ bit field in the DMACHCTL register. If only a single transfer is needed for a µDMA trigger, then
the ARBSIZ field is set to 0x1. If the trigger peripheral generates another µDMA request while the prior
one is being serviced and that particular channel is the highest priority asserted channel, the second
request is processed as soon as the handling of the first is complete. If two additional trigger peripheral
µDMA requests are generated prior to the completion of the first, the third request is lost.
4.2.7.3 Software Request
Few μDMA channels are dedicated to software-initiated transfers. This channel also has a dedicated
interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring and
enabling the transfer, and then issuing a software request using the DMA Channel Software Request
(DMASWREQ) register. For software-based transfers, use the auto transfer mode.
The DMASWREQ register can initiate a transfer on any channel. If a request is initiated by software using
a peripheral μDMA channel, then the completion interrupt occurs on the interrupt vector for the peripheral
instead of the software interrupt vector. Any channel may be used for software requests, as long as the
corresponding peripheral is not using μDMA for data transfer.
4.2.8 Interrupts and Errors
When a μDMA transfer is complete, a dma_done signal is sent to the peripheral that initiated the μDMA
event. Interrupts can be enabled within the peripheral to trigger on μDMA transfer completion. If the
transfer uses the software μDMA channel, then the completion interrupt occurs on the dedicated software
μDMA interrupt vector. If the μDMA controller encounters a bus or memory protection error as it attempts
to perform a data transfer, it disables the μDMA channel that caused the error and generates an interrupt
on the μDMA error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR)
register to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be
cleared by writing a 1 to the ERRCLR bit.
SWRU367D – June 2014 – Revised May 2018
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Functional Description
Direct Memory Access (DMA)
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