Spi_Chctrl Register - Texas Instruments CC3200 Technical Reference Manual

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8.6.1.8 SPI_CHCTRL Register (offset = 134h) [reset = 0h]
SPI_CHCTRL is shown in
This register enables the channel and defines the extended clock ratio with one clock cycle granularity.
31 30 29 28
15 14 13 12
EXTCLK
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-16 RESERVED
15-8 EXTCLK
7-1 RESERVED
0 EN
SWRU367D – June 2014 – Revised May 2018
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Figure 8-26 and described in
Figure 8-26. SPI_CHCTRL Register
27 26 25 24
RESERVED
11 10 9 8
R/W-0h
Table 8-14. SPI_CHCTRL Register Field Descriptions
Type Reset
R 0h
R/W 0h
R 0h
R/W 0h
Copyright © 2014–2018, Texas Instruments Incorporated
Table 8-14.
23 22 21 20
R-0h
7 6 5 4
RESERVED
R-0h
Description
Clock ratio extension
This register is used to concatenate with the SPI_CHCONF[CLKD]
register for the clock ratio only when the granularity is one clock
cycle (SPI_CHCONF[CLKG] set to 1). Then, the max value reached
is 4096 clock divider ratio.
0h = Clock ratio is CLKD + 1
1h = Clock ratio is CLKD + 1 + 16
FFh = Clock ratio is CLKD + 1 + 4080
Channel enable
0h = Channel is not active
1h = Channel is active
SPI Registers
19 18
3 2
SPI (Serial Peripheral Interface)
17 16
1 0
EN
R/W-
0h
281