Camclkcfg Register - Texas Instruments CC3200 Technical Reference Manual

PRCM Registers
15.7.1.1 CAMCLKCFG Register (offset = 0h) [reset = 0h]
CAMCLKCFG is shown in
31 30 29 28
15 14 13 12
RESERVED
R-0h
Bit Field
31-11 RESERVED
10-8 DIVOFFTIM
7-3 NU1
2-0 DIVONTIM
472
Power, Reset and Clock Management
Figure 15-4 and described in
Figure 15-4. CAMCLKCFG Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
DIVOFFTIM
R/W-0h
Table 15-4. CAMCLKCFG Register Field Descriptions
Type Reset
R 0h
R/W 0h
R 0h
R/W 0h
Copyright © 2014–2018, Texas Instruments Incorporated
Table 15-4.
23 22 21 20
7 6 5 4
NU1
R-0h
Description
CAMERA_PLLCKDIV_OFF_TIME Configuration of OFF-TIME for
dividing PLL clk (240 MHz) in generation of Camera func-clk:
000h = 1
001h = 2
010h = 3
011h = 4
100h = 5
101h = 6
110h = 7
111h = 8
CAMERA_PLLCKDIV_ON_TIME Configuration of ON-TIME for
dividing PLL clk (240 MHz) in generation of Camera func-clk:
000h = 1
001h = 2
010h = 3
011h = 4
100h = 5
101h = 6
110h = 7
111h = 8
SWRU367D – June 2014 – Revised May 2018
www.ti.com
19 18 17 16
3 2 1 0
DIVONTIM
R/W-0h
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