Samsung KS57C2308 Manual page 61

KS57C2308/P2308/C2316/P2316
LMOD
— LCD Mode Register
Bit
Identifier
Value
RESET
Read/Write
Bit Addressing
.7–.6
.5–.4
.3–.0
7 6
.7 .6
0 0
W W
8 8
LCD Output Segment and Pin Configuration Bits
0 0 Segments 24–27; and 28–31
0 1 Segment 24–27; 1-bit output at P8.4–P8.7
1 0 Segment 28–31; 1-bit output at P8.0–P8.3
1 1 1-bit output only at P8.0–P8.3, and P8.4–P8.7
LCD Clock (LCDCK) Frequency Selection Bits
9
0 0
fw/2 = 64 Hz
8
0 1
fw/2 = 128 Hz
7
1 0
fw/2 = 256 Hz
6
1 1
fw/2 = 512 Hz
NOTE: Assuming watch timer clock (fw) = 32.768 kHz.
Duty and Bias Selection for LCD Display
0 – – – LCD display off
1 0 0 0 1/4 duty, 1/3 bias
1 0 0 1 1/3 duty, 1/3 bias
1 0 1 0 1/2 duty, 1/2 bias
1 0 1 1 1/3 duty, 1/2 bias
1 1 0 0 Static
5 4 3
.5 .4 .3
0 0 0
W W W
8 8 1/8
MEMORY MAP
F8DH, F8CH
2 1 0
.2 .1 .0
0 0 0
W W W
8 8 8
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