Samsung KS57C2308 Manual page 253

KS57C2308/P2308/C2316/P2316
LCD MODE REGISTER (LMOD)
The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and
display on/off. LMOD can be manipulated using 8-bit write instructions, bit 3 (LMOD.3) can be also written by
1-bit instructions.
F8CH LMOD.3
F8DH LMOD.7
The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output which
is also referred to as the frame frequency. Since LCDCK is generated by dividing the watch timer clock (fw), the
watch timer must have been enabled when the LCD display is turned on.
to logic zero.
The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch
timer source and running. The LCD mode register LMOD controls the output mode of the 8 pins used for normal
outputs
(P8.0–P8.7). Bits LMOD.7–6 define the segment output and normal bit output configuration.
LMOD.7 LMOD.6
0 0
0 1
1 0
1 1
LMOD.5 LMOD.4
0 0
0 1
1 0
1 1
LMOD.3 LMOD.2
0 –
1 0
1 0
1 0
1 0
1 1
LMOD.2 LMOD.1
LMOD.6 LMOD.5
Table 12-4. LCD Mode Register (LMOD) Organization
LCD Output Segments and 1-Bit Output Pins
Segments 24–27, and 28–31
Segments 24–27; 1-bit output at P8.4–P8.7
Segments 28–31; 1-bit output at P8.0–P8.3
1-bit output only at P8.0–P8.3 and P8.4–P8.7
32.768 kHz watch timer clock (fw)/2
8
fw/2 = 128 Hz
7
fw/2 = 256 Hz
6
fw/2 = 512 Hz
LMOD.1 LMOD.0
– –
0 0
0 1
1 0
1 1
0 0
LMOD.0
LMOD.4
RESET
LCD Clock (LCDCK) Frequency
9
= 64 Hz
Duty and Bias Selection for LCD Display
LCD Display off
1/4 duty, 1/3 bias
1/3 duty, 1/3 bias
1/2 duty, 1/2 bias
1/3 duty, 1/2 bias
Static
LCD CONTROLLER/DRIVER
clears the LMOD register values
12-5