Samsung KS57C2308 Manual page 189

Single-chip cmos microcontroller
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KS57C2308/P2308/C2316/P2316
MULTIPLE INTERRUPTS
The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all
interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt
service routine for a lower-priority request is accepted during the execution of a higher priority routine.
Two-Level Interrupt Handling
Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits
of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all
interrupt requests are serviced (see Figure 7-3).
Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one and the values are stored in the
stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0
values are automatically restored from the stack by an IRET instruction.
IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable
memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable
interrupt processing with a DI instruction.
When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt
currently defined by the interrupt priority register (IPR).
INT Disable
SET IPR
INT Enable
Low or High
Level
Interrupt
Generated
Normal Program
Processing
(Status 0)
Figure 7-3. Two-Level Interrupt Handling
High or Low Level Interrupt
Processing
(Status 1)
High-Level
Interrupt
Generated
INTERRUPTS
High Level Interrupt
Processing
(Status 2)
7-5

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