Samsung KS57C2308 Manual page 191

KS57C2308/P2308/C2316/P2316
INTERRUPT PRIORITY REGISTER (IPR)
The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic
zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI
instruction.
FB2H IME
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or
you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by
a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by
any other interrupt source.
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if
an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the
IME flag is set to logic one. The IME flag (mapped FB2H.3) can be directly manipulated by EI and DI instructions,
regardless of the current enable memory bank (EMB) value.
IPR.2
0
0
0
0
1
1
NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more
interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt
priorities in Table 7-3 (the default priority assigned by hardware when the lower three IPR bits = "0"). In this case,
the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-priority
interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started.
IPR.2 IPR.1
Table 7-3. Standard Interrupt Priorities
Interrupt
INTB, INT4
INT0
INT1
INTS
INTT0
Table 7-4. Interrupt Priority Register Settings
IPR.1 IPR.0
0 0
0 1
1 0
1 1
0 0
0 1
IPR.0
Default Priority
1
2
3
4
5
Normal interrupt handling according to default priority settings
Process INTB and INT4 interrupts at highest priority
Process INT0 interrupts at highest priority
Process INT1 interrupts at highest priority
Process INTS interrupts at highest priority
Process INTT0 interrupts at highest priority
Result of IPR Bit Setting
INTERRUPTS
7-7