Samsung KS57C2308 Manual page 254

LCD CONTROLLER/DRIVER
Table 12-5. LCD Clock Signal (LCDCK), Frame Frequency and LCD sync Signal (LCDSY)
LCDCK frequency
9
fw/2 = 64 Hz
8 =
fw/2 128 Hz
7
fw/2 = 256 Hz
6
fw/2 = 512 Hz
NOTES:
1. fw = 32.768 kHz
2. The number in parentheses is a frequency for LCDSY.
LCD DRIVE VOLTAGE
LCD Power Supply
V
LC0
V
LC1
V
LC2
GND
NOTE: The LCD panel display may deteriorate if DC voltage is applied between the common and segment signals.
Therefore, always drive the LCD panel with AC voltage.
LCD VOLTAGE DIVIDING RESISTORS
On-chip voltage dividing resistors for the LCD drive power supply can be configured by internal voltage dividing
resistors. Using these internal voltage dividing resistors, you can drive either a 3 V or a 5 V LCD display using
external bias. Bias pins are connected externally to the V
voltages. To cut off the current supply to the voltage dividing resistors, clear LCON.0 when you turn the LCD
display off.
12-6
Static
64 (16)
128 (32)
256 (64)
512 (128)
Static Mode
V
LCD
2/3 V
LCD
1/3 V
LCD
0 V
LCD
KS57C2308/P2308/C2316/P2316
1/2 Duty 1/3 Duty
32 (16) 21 (21)
64 (32) 43 (43)
128 (64) 85 (85)
256 (128) 171 (171)
1/2 Bias
V
LCD
1/2 V
LCD
1/2 V
LCD
0 V
pin so that it can handle the different LCD drive
1/4 Duty
16 (16)
32 (32)
64 (64)
128 (128)
1/3 Bias
V
LCD
2/3 V
LCD
1/3 V
LCD
0 V