Altera Cyclone V Boot Manual page 9

AN-709
2016.01.27
A typical bare-metal application boot time is depicted in the following figure:
Figure 7: Boot Time Stages for a Bare-Metal Application
Note: The above figures are not drawn to scale - each stage is depicted with the same size.
Optimizing Boot Duration
The recommended approach for optimizing boot time consists of:
• Measure the duration of the total boot time. For example, monitor the reset signal and a custom signal
toggled at the beginning of the application by using a scope or a logical analyzer.
• Measure the duration of as many individual steps as possible, to understand where most of the time is
spent.
• If possible, optimize the steps that take most of the time. Usually the upper levels take longer than the
lower ones.
The following sections describe some of the factors that influence the duration of the Boot ROM.
Hardware Powerup Sequence
This is the smallest contributor to boot time and it does not need to be optimized. It is actually influenced
by the
OSC1
value.
Boot ROM
The duration of the Boot ROM is influenced by the following factors:
• Clock Frequency (for the portion before setting the PLLs or when using
OSC1
• Clocking option (selected by
• Boot Source (SD/MMC, QSPI, NAND or FPGA – selected by
• Performance of external flash device
• Size of Preloader image
The above parameters can be tweaked in order to optimize the Boot ROM duration. For example, the
and should be selected such that the maximum possible clock values are used for both the MPU and
CSEL
the external flash.
Another example - Tweaking the Preloader so that it is made smaller. The smaller the Preloader, the less
time the Boot ROM spends loading it from flash.
HPS SoC Boot Guide - Cyclone V SoC Development Kit
Send Feedback
input clock frequency, but it is so small that its duration does not warrant changing the
CSEL
pins)
Optimizing Boot Duration
)
CSEL=00
pins)
BSEL
9
OSC1
OSC1
Altera Corporation