Altera Cyclone V Boot Manual page 8

8
Boot Duration
In order to accommodate the above, the Boot ROM can be instructed to use different clocking options,
through the CSEL pins. The following table presents the CSEL options available on Cyclone V, together
with the actual jumper settings on the Cyclone V Development Kit, rev D:
Table 1: CSEL Options Available
CSEL
0
1
2
3
Note: In the following cases the Boot ROM does not touch the clocking at all:
• CSEL = 0
• Boot from FPGA
• Fallback boot from FPGA
• RAM boot on Warm reset
Related Information
Booting and Configuration
For more information about what each of the CSEL values mean for each of the BSEL options, refer to the
Booting and Configuration chapter of the Cyclone V Technical Reference Manual.
Boot Duration
In some applications, the duration of the boot process is very critical, and it needs to meet a certain
constraint.
This section presents some considerations on optimizing the boot time, together with some measurements
taken with various options on the Cyclone V Development Kit.
The elements that compose the boot time for a typical Linux system are depicted in the figure below:
Figure 6: Boot Time Stages for Linux Systems
Altera Corporation
J26:CSEL0
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Cyclone V Dev Kit Switches
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HPS SoC Boot Guide - Cyclone V SoC Development Kit
2016.01.27
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