Keysight Technologies N5171B EXG User Manual page 303

1. The IF signal type is not available for a serial port configuration.
Table 10-2 Warranted Parallel Input Level Clock Rates and Maximum Clock Rates
Logic Type
LVTTL and CMOS
LVDS
The levels will degrade above the warranted level clock rates, but they may still be usable.
Serial Port Configuration Clock Rates
For a serial port configuration, the lower clock rate limit is determined by the word size (word size
and sample size are synonymous), while the maximum clock rate limit remains constant at 150 MHz
for LVTTL and CMOS logic types, and 400 MHz for an LVDS logic type.
The reverse is true for the sample rate. The lower sample (word) rate value of 1 kHz remains while
the upper limit of the sample rate varies with the word size. For example, a five-bit sample for an
LVTTL or CMOS logic type yields the following values in serial mode:
— Clock rate of 5 kHz through 150 MHz
— Sample rate of 1 kHz through 30 MHz
Refer to Table 10-3 and
Table 10-3 Output Serial Clock Rates
Logic Type
LVDS
LVTTL and CMOS
Table 10-4 Input Serial Clock Rates
Logic Type
LVDS
LVTTL and CMOS
1. The maximum sample rate depends on the selected filter when the data rate is Pre-FIR Samples.
Refer to "Input Mode" on page 299
Keysight EXG and MXG X-Series Signal Generators User's Guide
Warranted Level Clock Rates
100 MHz
200 MHz
Table 10-4, for the serial clock rates.
Minimum Rate
1 x (word size) kHz
1 x (word size) kHz
Data Type Minimum Rate
Samples 1 x (word size) kHz
Pre-FIR 1 x (word size) kHz
Samples
N/A 1 x (word size) kHz
Digital Signal Interface Module (Option 003/004)
Maximum Clock Rates (typical)
150 MHz
200 MHz
Maximum Rate
400 MHz
150 MHz
Maximum Rate
400
the smaller of: 50
or
400 MHz
150 MHz
for more information.
Clock Timing
1
x (word size) MHz
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