ICP DAS USA PCI-1002L User Manual page 49

PCI-1002 Series Card
12-bit, 110 kS/s or 44 kS/s Multi-function Board
6.2.2.4 The Status Register
Address 10h is used by the status register. Reading from this address will get the data from the
status register. The format of status register is:
Bit 7 - Bit 6 Bit 5
Gain Control 8254
Timer 1
Bit 7-6 : Current AD gain control.
Bit 5 : Output of 8254 timer 1.
Bit 4 : Output of 8254 timer 0.
Bit 3 : Output of 8254 timer 2.
Bit 2 : Reserved. Used for hardware testing.
Bit 1 : Analog input type, '1' indicates that analog input type is single-ended and '0'
indicates analog input is differential.
Bit 0 : AD ready signal. '0' indicates not ready, AD is under conversion. '1' indicates ready, AD is
completely converted and is idle now.
6.2.2.5 The AD Software Trigger Register
Writing to this port (1Ch) will generate an AD trigger pulse signal.
Note: Although a very fast trigger can be performed (more than the speed of AD controller, 110 K) via this method, a
reasonable delay time should be left between the two triggers.
Software
trigger
AD
Busy
Figure 6-1: Software trigger delay time.
Bit 4 Bit 3
8254 8254
Timer 0 Timer 2
Delay time
8 µs
Conversion Time
User Manual, Ver. 3.0, Jun. 2018, PMH-015-30, Page: 48
Bit 2 Bit 1
Reserved Analog Input
Type
Bit 0
AD Ready