Diamond Systems Hercules III User Manual page 54

High integration ebx sbc with data acquisition & dc power supply
Table of Contents

Advertisement

Operation Status: Base+14 (Read)
Bit:
7
Name:
-
TINT
Timer interrupt status:
1 = interrupt pending
0 = no interrupt pending
DINT
Digital I/O interrupt status:
1 = interrupt pending
0 = no interrupt pending
AINT
A/D interrupt status:
1 = interrupt pending
0 = no interrupt pending
FIFO overflow flag. Overflow occurs when the FIFO is full and an A/D conversion occurs. If
OVF
OVF is set, it will stay set until the FIFO is reset with a FIFORST command.
0 = no overflow
1 = overflow
FF
FIFO full flag:
0 = FIFO is not full
1 = FIFO is full
TF
FIFO threshold flag:
0 = FIFO depth is below the programmed threshold
1 = FIFO depth is at or above the programmed threshold
EF
FIFO empty flag:
0 = not empty
1 = empty
Command: Base+15 (Write)
Bit:
7
Name:
-
FIFORST Reset the FIFO. After this command, OVF, FF, and TF = 0, and EF = 1.
DARST
Reset the D/A. All D/A channels are reset to zero-scale.
CLRT
Clear timer interrupt request.
CLRD
Clear digital I/O interrupt request.
CLRA
Clear A/D interrupt request.
ADSTART Start an A/D conversion. After this command, ADBUSY = 1, until the A/D conversion is
finished.
Each bit in this register represents a command. Writing a 1 to any bit executes the command specified
by that bit. Only one bit may be written at a time.
Hercules III User Manual Rev A.2
6
5
TINT
DINT
AINT
6
5
-
FIFORST
DARST
www.diamondsystems.com
4
3
2
OVF
FF
4
3
2
CLRT
CLRD
1
0
TF
EF
1
0
CLRA
ADSTART
Page
54

Advertisement

Table of Contents
loading

Table of Contents