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Page 1 Read
Offset base+31 is the FPGA revision code (0x40).
Base +
0
PWMD7
24
PWMD15
25
26
PWMD23
27
28
29
30
31
Page 2 Write
Offsets base+24 through base+31 are reserved for a future D/A waveform generator circuit.
Base +
HOLDOFF
0
24
25
26
27
28
29
30
31
Page 2 Read
Base +
0
ADQ7
24
FDID2
25
26
DIOQ7
PWMQ3
27
28
29
30
31
Hercules III User Manual Rev A.2
7
6
5
-
-
-
PWMD6
PWMD5
PWMD14
PWMD13 PWMD12
PWMD22
PWMD21 PWMD20 PWMD19 PWMD18
-
-
-
D7
D6
D5
-
A6
A5
0
TDBUSE
EEBUSY
-
-
-
7
6
5
RESET
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
6
5
-
-
-
ADQ6
ADQ5
FDID1
FDID0
DIOQ6
DIOQ5
PWMQ2
PWMQ1
ID7
ID6
ID5
ID15
ID14
ID13
-
-
-
-
-
-
www.diamondsystems.com
4
3
2
-
-
-
PWMD4
PWMD3
PWMD2
PWMD11
PWMD10
-
-
-
D4
D3
D2
A4
A3
A2
CMUXEN
0
0
-
-
-
4
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
3
2
-
-
-
ADQ4
ADQ3
ADQ2
DAQ4
DAQ3
DAQ2
DIOQ4
DIOQ3
DIOQ2
PWMQ0
CTRQ3
CTRQ2
ID4
ID3
ID2
ID12
ID11
ID10
-
-
-
-
-
-
1
0
-
-
PWMD1
PWMD0
PWMD9
PWMD8
PWMD17 PWMD16
-
-
D1
D0
A1
A0
0
0
-
-
1
0
PAGE1
PAGE0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
-
-
ADQ1
ADQ0
DAQ1
DAQ0
DIOQ1
DIOQ0
CTRQ1
CTRQ0
ID1
ID0
ID9
ID8
-
-
-
-
Page
47
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