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A/D MSB: Base+1 (Read)
Bit:
7
Name:
AD15
AD15-AD8 A/D MSB data. The A/D data must be read LSB first, followed by MSB.
A/D Low Channel: Base+2 (Read/Write)
Bit:
7
Name:
-
L4-L0
A/D low channel number.
A/D High Channel: Base+3 (Read/Write)
Bit:
7
Name:
-
H4-H0
A/D high channel number.
A/D Input Range Control: Base+4 (Write)
Bit:
7
Name:
LDAD
The FPGA contains a global input range setting as well as a 32x4 table for all 32 input
LDAD
channels that can be used for individual input ranges, for each channel. The chip uses either
the global input range setting or the individual range table, based on the setting of the
SINGLE bit in register Base+12.
If this bit is set (1), the remaining bits are stored as the individual input range for the A/D
channel currently set by L4-L0 in register Base+2. If this bit is reset (0), the remaining bits
are the global setting for all input channels.
G(1/0)
Gain: The gain is the ratio between the input voltage and the voltage seen by the A/D
converter. The A/D always works with a maximum input voltage of 10V. A gain of 2 means
the maximum input voltage at the connector pin is 5V.
0 = gain of 1
1 = gain of 2
2 = gain of 4
3 = gain of 8
Hercules III User Manual Rev A.2
6
5
AD14
AD13
AD12
6
5
-
-
6
5
-
-
6
5
-
-
www.diamondsystems.com
4
3
2
AD11
AD10
4
3
2
L4
L3
L2
4
3
2
H4
H3
H2
4
3
2
-
-
-
1
0
AD9
AD8
1
0
L1
L0
1
0
H1
H0
1
0
G(1/0)
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