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I/O Register Definitions
Page 0 Register Definitions
Page Select and Reset Command: Base+0 (Write)
Bit:
7
Name:
HOLDOFF
HOLDOFF
When this bit is set, the chip ignores any data written to this register. This bit enables
RESET
Reset the entire data acquisition circuit. After a reset, the following conditions are true:
Digital I/O ports are set to input mode and all output registers are cleared to 0.
1.
A/D channel registers and range settings are cleared to zero, except for the Analog
2.
Configuration Register (Base+1) which is set to 0x04.
D/A channels are cleared to mid-scale or zero-scale, depending on the board jumper
3.
setting.
Counter/timers are disabled and counter registers are cleared to zero.
4.
Watchdog timer is disabled and timer registers are cleared to zero.
5.
FIFO is reset, causing all contents to be lost, and threshold is set to 1024 samples.
6.
The internal channel / gain table is reset to all zeros.
7.
PAGE
Select page.
0 = Main features page
1 = Extended features page
2 = ID page
3 = Copyright notice page
A/D LSB: Base+0 (Read)
Bit:
7
Name:
AD7
AD7-AD0 A/D LSB data. The A/D data must be read LSB first, followed by MSB.
Analog Configuration: Base+1 (Write)
Bit:
7
Name:
-
DABU
D/A output range: 0 = bipolar, 1 = unipolar. (Default on reset is unipolar mode).
SEDIFF A/D mode: 0 = single-ended, 1 = differential.
ADBU
A/D input range: 0 = bipolar, 1 = unipolar.
Hercules III User Manual Rev A.2
6
5
RESET
-
shadowing this register with another device at the same address.
6
5
AD6
AD5
6
5
-
-
www.diamondsystems.com
4
3
-
-
4
3
AD4
AD3
AD2
4
3
-
-
DABU
2
1
0
-
PAGE
2
1
0
AD1
AD0
2
1
0
SEDIFF
ADBU
Page
48
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