Atmel AT91SAM9G45-EKES User Manual page 55

8 7
{7,10,12} PA[0..31]
MN5A MN5A
L1
PA0
PA0/MCI0_CK/TCLK3
PA1 M1
PA1/MCI0_CDA/TIOA3
PA2 L5
PA2/MCI0_DA0/TIOB3
PA3 N1
PA3/MCI0_DA1/TCKL4
PA4 L6
PA4/MCI0_DA2/TIOA4
PA5 M2
PA5/MCI0_DA3/TIOB4
PA6 M3
PA6/MCI0_DA4/ETX2
M4
PA7
PA7/MCI0_DA5/ETX3
PA8 L7
PA8/MCI0_DA6/ERX2
N2
PA9
PA9/MCI0_DA7/ERX3
PA10 M5
PA10/ETX0
PA11 P1
D PA11/ETX1
PA12 N3
PA12/ERX0
PA13 P2
PA13/ERX1
M6
PA14
PA14/ETXEN
PA15 N4
PA15/ERXDV
N5
PA16
PA16/ERXER
PA17 N6
PA17/ETXCK
R1
PA18
PA18/EMDC
PA19 P3
PA19/EMDIO
PA20 R2
PA20/TW D0
P4
PA21
PA21/TW CK0
PA22 T1
PA22/MCI1_CDA/SCK3
P5
PA23
PA23/MCI1_DA0/RTS3
PA24 R3
PA24/MCI1_DA1/CTS3
T2
PA25
PA25/MCI1_DA2/PW M3
PA26 T3
PA26/MCI1_DA3/TIOB2
PA27 U1
PA27/MCI1_DA4/ETXER
PA28 U3
PA28/MCI1_DA5/ERXCK
PA29 U2
PA29/MCI1_DA6/ECRS
PA30 R4
PA30/MCI1_DA7/ECOL
PA31 V1
PA31/MCI1_CK/PCK0
MN5G MN5G
{4} EBI0_D[0..15]
EBI0_D0 R16
EBI0_DDR_D0
R15
EBI0_D1
EBI0_DDR_D1
EBI0_D2 T14
EBI0_DDR_D2
C EBI0_D3 P15
EBI0_DDR_D3
EBI0_D4 P16
EBI0_DDR_D4
EBI0_D5 P17
EBI0_DDR_D5
EBI0_D6 R14
EBI0_DDR_D6
EBI0_D7 P14
EBI0_DDR_D7
N15
EBI0_D8
EBI0_DDR_D8
EBI0_D9 N16
EBI0_DDR_D9
P18
EBI0_D10
EBI0_DDR_D10
EBI0_D11 N17
EBI0_DDR_D11
N18
EBI0_D12
EBI0_DDR_D12
EBI0_D13 N14
EBI0_DDR_D13
EBI0_D14 M15
EBI0_DDR_D14
M16
EBI0_D15
EBI0_DDR_D15
{4} EBI0_A[0..13]
EBI0_A0 M17
EBI0_DDR_A0
L14
EBI0_A1
EBI0_DDR_A1
EBI0_A2 M18
EBI0_DDR_A2
EBI0_A3 L15
EBI0_DDR_A3
EBI0_A4 L16
EBI0_DDR_A4
EBI0_A5 L18
EBI0_DDR_A5
L17
EBI0_A6
EBI0_DDR_A6
EBI0_A7 K14
EBI0_DDR_A7
K15
EBI0_A8
EBI0_DDR_A8
EBI0_A9 K16
EBI0_DDR_A9
EBI0_A10 K18
EBI0_DDR_A10
EBI0_A11 K17
EBI0_DDR_A11
EBI0_A12 J14
EBI0_DDR_A12
EBI0_A13 J15
EBI0_DDR_A13
B
G17
{4} EBI0_BA0
EBI0_DDR_BA0
G16
{4} EBI0_BA1 EBI0_DDR_BA1
J16
{4} EBI0_CKE
EBI0_DDR_CKE
J18
{4} EBI0_CLK EBI0_DDR_CLK
H18
{4} EBI0_NCLK
EBI0_DDR_NCLK
H14
{4} EBI0_CS EBI0_DDR_CS
H17
{4} EBI0_CAS EBI0_DDR_CAS
J17
{4} EBI0_RAS
EBI0_DDR_RAS
H15
{4} EBI0_WE
EBI0_DDR_W E
A16
{5,6} DDR_VREF EBI0_DDR_VREF
G14
{4} EBI0_DQM0 EBI0_DDR_DQM0
H16
{4} EBI0_DQM1
EBI0_DDR_DQM1
G18
{4} EBI0_DQS0 EBI0_DDR_DQS0
G15
{4} EBI0_DQS1
EBI0_DDR_DQS1
A
8 7
6
PB[0..31] {2,7,9,12}
MN5B MN5B
T4
PB0
PB0/SPI0_MISO
V2 PB1
PB1/SPI0_MOSI
V3 PB2
PB2/SPI0_SPCK
U4 PB3
{4,6} PC[2..5]
PB3/SPI0_NPCS0
R5 PB4
PB4/TXD1
V4 PB5
PB5/RXD1
T5 PB6
PB6/TXD2
U5
PB7
PB7/RXD2
T12 PB8
PB8/TXD3/ISI_D8
N11
PB9
PB9/RXD3/ISI_D9
U13 PB10
PB10/TW D1/ISI_D10
M11 PB11
PB11/TW CK1/ISI_D11 {6} PC8
P6 PB12
PB12/DRXD
R6 PB13
PB13/DTXD
M7
PB14
PB14/SPI1_MISO
V5 PB15
PB15/SPI1_MOSI/CTS0
T6
PB16
PB16/SPI1_SPCK/SCK0
U6 PB17
PB17/SPI1_NPCS0/RTS0 {6} PC14
N7
PB18
PB18/RXD0/SPI0_NPCS1
P7 PB19
PB19/TXD0/SPI0_NPCS2
P12 PB20
PB20/ISI_D0
T15
PB21
PB21/ISI_D1
R12 PB22
PB22/ISI_D2
T16
PB23
PB23/ISI_D3
N12 PB24
PB24/ISI_D4
M12
PB25
PB25/ISI_D5
U14 PB26
PB26/ISI_D6
M13 PB27
PB27/ISI_D7
N13 PB28
PB28/ISI_D8
R13 PB29
PB29/ISI_VSYNC
T13 PB30
PB30/ISI_HSYNC
P13 PB31
PB31/ISI_MCK/PCK1
EBI1_D[0..15]
MN5F MN5F
A17 EBI1_D0
EBI1_A[1..18]
EBI1_D0
D15 EBI1_D1
EBI1_D1
C15
EBI1_D2
EBI1_D2
B16 EBI1_D3
EBI1_D3
B15 EBI1_D4
EBI1_D4
D14 EBI1_D5
EBI1_D5
C14 EBI1_D6
EBI1_D6
A15 EBI1_D7
EBI1_D7
B14 EBI1_D8
EBI1_D8
D13
EBI1_D9
EBI1_D9
C13 EBI1_D10
EBI1_D10
E13
EBI1_D11
EBI1_D11
B13 EBI1_D12
EBI1_D12
E12
EBI1_D13
EBI1_D13
D12 EBI1_D14
EBI1_D14
C12 EBI1_D15
EBI1_D15
F13 EBI1_A0 EBI1_A0
EBI1_NBS0/A0
F14
EBI1_A1
EBI1_NBS2/NW R2/A1
F18 EBI1_A2
EBI1_A2
F15
EBI1_A3
EBI1_A3
E14 EBI1_A4
EBI1_A4
F17 EBI1_A5
EBI1_A5
F16 EBI1_A6
EBI1_A6
E17 EBI1_A7
EBI1_A7
E15
EBI1_A8
EBI1_A8
E16 EBI1_A9
EBI1_A9
D18
EBI1_A10
EBI1_A10
D17 EBI1_A11
EBI1_A11
C18 EBI1_A12
EBI1_A12
B18 EBI1_A13
EBI1_A13
A18 EBI1_A14
EBI1_A14
B17 EBI1_A15
EBI1_A15
C10 EBI1_A16
EBI1_BA0/A16
B10
EBI1_A17
EBI1_BA1/A17
C17 EBI1_A18
EBI1_A18
B11
EBI1_DQM0 {4}
EBI1_DQM0
D11
EBI1_DQM1 {4}
EBI1_DQM1
A11
EBI1_DQS0 {4}
EBI1_DQS0
E11
EBI1_DQS1 {4}
EBI1_DQS1
A12
EBI1_RAS {4}
EBI1_RAS
C11
EBI1_CAS {4}
EBI1_CAS
F12
EBI1_SDWE {4}
EBI1_SDW E
B9
EBI1_SDA10 {4}
EBI1_SDA10
B12
EBI1_SDCKE {4}
EBI1_SDCKE
A13
EBI1_SDCK {4}
EBI1_SDCK
A14
EBI1_NSDCK {4}
EBI1_NSDCK
A10
EBI1_NCS0 EBI1_NCS0 {6}
F10
EBI1_NCS1/SDCS {4}
EBI1_NCS1/SDCS
F11
EBI1_NRD/CFOE {6}
EBI1_NRD/CFOE
C9
EBI1_NWE/NWR0/CFWE
EBI1_NW E/NW R0/CFW E
D9
EBI1_NBS1/NW R1/CFIOR
A9
EBI1_NBS3/NW R3/CFIOW
D10
EBI1_NANDOE {6}
EBI1_NANDOE
E10
EBI1_NANDWE {6}
EBI1_NANDW E
6
5 4
MN5C MN5C MN5D MN5D
A8
PC0/DQM2 PD0/TK0/PW M3
E9
PC1/DQM3
PC2 B8
PC2/A19
PC3 C8
PC3/A20
F9
PC4
PC4/A21/NANDALE
PC5 A7
PC5/A22/NANDCLE
D8
PC6/A23
A6
PC7/A24 PD7/AC97TX/TIOA5
PC8 E8
PC8/CFCE1 PD8/AC97FS/TIOB5
C7
PC9/CFCE2/RTS2 PD9/97CK/TCLK5
B6
PC10/NCS4/CFCS0/TCLK2
B7
PC11/NCS5/CFCS1/CTS2
A5
PC12/A25/CFRNW PD12/TK1/PCK0
D7
PC13/NCS2
PC14 F8
PC14/NCS3/NANDCS
C6
PC15/NW AIT
E7
PC16/D16
B5
PC17/D17
D6
PC18/D18 PD18/SPI1_NPCS2/IRQ
F7
PC19/D19 PD19/SPI0_NPCS3/FIQ
A4
PC20/D20
C5
PC21/D21
B4
PC22/D22
E6
PC23/D23
D5
PC24/D24 PD24/SPI0_NPCS1/PW M0
A3
PC25/D25 PD25/SPI0_NPCS2/PW M1
C4
PC26/D26 PD26/PCK0/PW M2
A1
PC27/D27 PD27/PCK1/SPI0_NPCS3
A2
PC28/D28 PD28/TSADTRG/SPI1_NPCS1
B2
PC29/D29 PD29/TCLK1/SCK1
B3
PC30/D30 PD30/TIOB0/SCK2
B1
PC31/D31 PD31/TIOB1/PW M1
{4}
{4}
T18
R16 R16 39R 39R
R18
R17 R17 39R 39R
T17
{9} HDPA
R17
{9} HDMA
R18 R18 39R 39R V15
V16
TP6 TP6
R19 R19 39R 39R
U15
TESTPOINT TESTPOINT
{9} HDPB
U16
{9} HDMB
U11
{2} VDDOSC
U12
C32 C32
100nF 100nF
V12
C34 C34
18pF 18pF
Y1 Y1
C38 C38
12 MHz 12 MHz
18pF 18pF V11
C41 C41 C1
15pF 15pF
Y2 Y2
32.768 kHz 32.768 kHz
C45 C45 D1
15pF 15pF
VDDBU R20 R20 DNP DNP E4
NTRST N10
{9} NTRST
R10
TDI
{9} TDI
TMS P10
{9} TMS
U10
TCK
{9} TCK
RTCK R11
{9} RTCK
TDO V10
{9} TDO
NRST M10
{2,7,8,9,10,12} NRST
F3
{2} SHDN
{6}
{2} WAKE UP
SUP1 SUP1
BOOT MODE SELECT
Opened = Internal ROM BOOT
Closed = NCS0
DNP DNP
SG-BGA-CA89405MF SG-BGA-CA89405MF
5 4
3 2
{8,11,12} PE[0..31]
PE0
PE1
PE2
PD[0..31] {2,7,8,9,10,11,12}
R7 PD0 PE3
T7 PD1 PE4
PD1/TF0
L8 PD2 PE5
PD2/TD0
V6 PD3 PE6
PD3/RD0
M8
PD4 PE7
PD4/RK0
V7 PD5 PE8
PD5/RF0
N8
PD6 PE9
PD6/AC97RX
U7 PD7 PE10
P8 PD8 PE11
R8 PD9 PE12
U8 PD10 PE13
PD10/TD1
T8
PD11 PE14
PD11/RD1
V8 PD12 PE15
L9
PD13 PE16
PD13/RK1
U9 PD14 PE17
PD14/TF1
M9
PD15 PE18
PD15/RF1
N9 PD16 PE19
PD16/RTS1
V9 PD17 PE20
PD17/CTS1
R9
PD18 PE21
T9 PD19 PE22
D2
PD20 PE23
PD20/TIOA0
E1 PD21 PE24
PD21/TIOA1
F1
PD22 PE25
PD22/TIOA2
G2 PD23 PE26
PD23/TCLK0
F2 PD24 PE27
G1 PD25 PE28
H1 PD26 PE29
H2 PD27 PE30
P9 PD28 PE31
L10
PD29
T10 PD30
L11 PD31
MN5H MN5H
HFSDPA VDDBU
HFSDMA GNDBU
HHSDPA VDDPLLUTMI
HHSDMA VDDUTMIC
DFSDP/HFSDPB GNDUTMI
DFSDM/HFSDMB
VDDUTMII
DHSDP/HHSDPB
DHSDM/HHSDMB
VDDIOP0
VDDOSC VDDIOP0
GNDOSC
VDDIOP1
XIN VDDIOP2
VDDCORE
VDDCORE
XOUT VDDCORE
VDDCORE
XIN32
VDDIOM0
VDDIOM0
VDDIOM0
XOUT32 VDDIOM0
VDDIOM1
VDDIOM1
JTAGSEL VDDIOM1
NTRST VDDIOM1
TDI
TMS
TCK VDDPLLA
RTCK
TDO
NRST TSADVREF
VDDANA
SHDN
GNDANA
3V3 R24 R24
10K 10K
R25 R25
4.7K 4.7K
JP8 JP8
AT91SAM9M10-EKES AT91SAM9M10-EKES AT91SAM9M10-EKES
AT91SAM9G45-EKES AT91SAM9G45-EKES AT91SAM9G45-EKES
SAM9 chip SAM9 chip SAM9 chip
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
3 2
1
MN5E MN5E
G4
PE0/LCDPW R/PCK0
F4
PE1/LCDMOD
G5
PE2/LCDCC
F5
PE3/LCDVSYNC
G7
PE4/LCDHSYNC
H5
PE5/LCDDOTCK
G3
PE6/LCDDEN
H6
PE7/LCDD0/LCDD2
G6
PE8/LCDD1/LCDD3
H7
PE9/LCDD2/LCDD4
H8
PE10/LCDD3/LCDD5
G8
PE11/LCDD4/LCDD6 D
J5
PE12/LCDD5/LCDD7
H4
PE13/LCDD6/LCDD10
J3
PE14/LCDD7/LCDD11
J4
PE15/LCDD8/LCDD12
J2
PE16/LCDD9/LCDD13
J6
PE17/LCDD10/LCDD14
J7
PE18/LCDD11/LCDD15
J1
PE19/LCDD12/LCDD18
J8
PE20/LCDD13/LCDD19
K1
PE21/LCDD14/LCDD20
K4
PE22/LCDD15/LCDD21
K2
PE23/LCDD16/LCDD22
K5
PE24/LCDD17/LCDD23
K6
PE25/LCDD18
K3
PE26/LCDD19
K7
PE27/LCDD20
K8
PE28/LCDD21
L3
PE29/LCDD22
L2
PE30/LCDD23
L4
PE31/PW M2/PCK1
C
VDDBU {2}
D4
C26 C26 100nF 100nF
D3
VDDPLLUTMI {2}
V13
C27 C27 100nF 100nF
U18
C28 C28 100nF 100nF
VDDUTMIC {2}
U17
VDDUTMII {2}
V17
C29 C29 100nF 100nF
VDDIOP0 {2}
K9
C30 C30
100nF 100nF
K10
C31 C31 100nF 100nF
VDDIOP1 {2}
H3
C33 C33 100nF 100nF
VDDIOP2 {2,12}
V14
C35 C35 100nF 100nF
VDDCORE {2}
E18
C36 C36 100nF 100nF
G12
C37 C37
100nF 100nF
G13
C39 C39
100nF 100nF
H11
C40 C40 100nF 100nF
VDDIOM0 {2}
K13
C42 C42 100nF 100nF
L12
C43 C43 B
100nF 100nF
L13
C44 C44 100nF 100nF
M14
C46 C46
100nF 100nF
VDDIOM1 {2}
D16
C47 C47 100nF 100nF
F6
C48 C48
100nF 100nF
G10
C49 C49 100nF 100nF
G11
C50 C50
100nF 100nF
VDDPLLA {2}
P11
C51 C51
100nF 100nF
E2
0R 0R R21 R21
E3
VDDANA {2}
C2 C52 C52 C53 C53
100nF 100nF 100nF 100nF
R22 R22
0R 0R
A
E E E LN LN LN 03-sep-09 03-sep-09 03-sep-09
PP PP PP 22-jun-09 22-jun-09 22-jun-09
D D D
C C C PP PP PP 02-DEC-08 02-DEC-08 02-DEC-08
29-JUL-08 29-JUL-08 29-JUL-08
B B B PP PP PP
A A A INIT EDIT INIT EDIT INIT EDIT PP PP PP 26-MAY-08 26-MAY-08 26-MAY-08 XXX XXX XXX XX-XXX-XX XX-XXX-XX XX-XXX-XX
REV REV REV MODIF. MODIF. MODIF. DES. DES. DES. DATE DATE DATE VER. VER. VER. DATE DATE DATE
1/1 1/1 1/1
SCALE SCALE SCALE REV. REV. REV. SHEET SHEET SHEET
3 3 3
E E E
12 12 12
1