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MISCSR3 – Miscellaneous Control Register #3
This register enables software to "push" the reset button.
Bits
Identifier
7
PROCHOT
6
LVDS_OC
3-5
Reserved
2
PBRESET
1-0
Reserved
EPU-3311 Programmer's Reference Manual
Table 11: MISCSR3 – Misc. Control Register #3
Access
Default
The status of the THERMTRIP signal from the CPU module.
RO
N/A
0 – THERMTRIP is not asserted (not hot)
1 – THERMTRIP is asserted
The overcurrent status from the LVDS panel power switch. If this is
ever asserted, the LVDS panel enable signal must be de-asserted
and then asserted to "unlatch" the power fault condition on the
RO
N/A
power switch.
0 – LVDS Overcurrent is not asserted
1 – LVDS Overcurrent is asserted
Reads the overcurrent status for the USB paddleboard power
switches (there are two power switches for the four ports but they
have a common overcurrent status).
RO
N/A
0 – Overcurrent is not asserted (power switch is on)
1 – Overcurrent is asserted (power switch is off)
When written to, this will do the same thing as pushing the reset
button, which could be useful for a software-initiated watchdog.
0 – No action
R/W
---
1 – Activate the reset push-button
Note: Because this generates a reset that will reset this register, it
isn't likely a value of a '1' can ever be read-back, so it is somewhat
"write-only".
RO
00
Reserved. Writes are ignored; reads always return 0.
FPGA Registers
Description
13
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