Table 27: Auxmode1 – Aux I/O Mode Register - VersaLogic Viper Programmer's Reference Manual

FPGA Registers
AUXMODE1– AUX I/O Mode Register #1
These two registers selected the mode on each AUX GPIO. This reset depends on the state of the
AUX_PSEN signal. If AUX_PSEN is a '0' then the reset is the power-on and Platform Reset. If
AUX_PSEN is a '1' then this register is only reset at power-on.
Table 27: AUXMODE1 – AUX I/O Mode Register
Bit Identifier
7 MODE_GPIO8
6 MODE_GPIO7
5 MODE_GPIO6
4 MODE_GPIO5
3 MODE_GPIO4
2 MODE_GPIO3
1 MODE_GPIO2
0 MODE_GPIO1
28
Access Default
GPIO 8 Mode:
R/W
0 0 – GPIO (I/O)
1 – ICTC3 (Input clock for Timer 3)
GPIO 7 Mode:
R/W
0 0 – GPIO (I/O)
1 – ICTC4 (Input clock for Timer 4)
GPIO 6 Mode:
R/W
0 0 – GPIO (I/O)
1 – OCTC3 (Output for Timer 3)
GPIO 5 Mode:
R/W
0 0 – GPIO (I/O)
1 – OCTC4 (Output for Timer 4)
GPIO 4 Mode:
R/W
0 0 – GPIO (I/O)
1 – GCTC3 (Input gate for Timer 3)
GPIO 3 Mode:
R/W
0 0 – GPIO (I/O)
1 – GCTC4 (Input gate for Timer 4)
GPIO 2 Mode:
R/W
0 0 – GPIO (I/O)
1 – SLEEP# (Output, active low SLEEP now signal)
GPIO 1 Mode:
R/W
0 0 – GPIO (I/O)
1 – WAKE# (Input, active low WAKE up signal)
Description
VL-EBX-38 Programmer's Reference Manual