Table 35: Tempicr – Temperature Interrupt Control Register - VersaLogic Viper Programmer's Reference Manual

TEMPICR – Temperature Interrupt Control Register
This is the interrupt mask register for the temperature sensor thermal alerts and the DDR3L
SODIMM EVENT signals and the interrupt enable and selection. The SODIMM may not have
any temperature event capability.
Reset type is Platform.
Table 35: TEMPICR – Temperature Interrupt Control Register
Bits Identifier
7 IRQEN
6-4 IRQSEL(2:0)
3 IMASK_BATTLOW
2 IMASK_EVENT
1 IMASK_THERM
0 IMASK_ALERT
TEMPISTAT – Temperature Interrupt Status Register
This is the interrupt status register for the temperature interrupt sources. It also contains
the battery low input status.
VL-EBX-38 Programmer's Reference Manual
Access Default
Temperature interrupt enable/disable:
R/W
0 0 – Interrupts disabled
1 – Interrupts enabled
Temperature interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
R/W
000
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
Battery-low interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
SODIMM EVENT output interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
Temperature Sensor THERM output interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
Temperature Sensor ALERT output interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
FPGA Registers
Description
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